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| author | Jack Koenig | 2021-07-07 16:56:35 -0700 |
|---|---|---|
| committer | GitHub | 2021-07-07 16:56:35 -0700 |
| commit | 558df41db062a14f52617fc44edd0aff569afa67 (patch) | |
| tree | ca560b875761ee798626dc55319d87e8240a5cde /core | |
| parent | 503ae520e7f997bcbc639b79869c9a4214d402ed (diff) | |
Fix ChiselEnum docs (#2016)
Also add newline to end of `verilog` modifier code blocks so that there
is always a newline between code blocks and following material.
Diffstat (limited to 'core')
0 files changed, 0 insertions, 0 deletions