summaryrefslogtreecommitdiff
path: root/core
diff options
context:
space:
mode:
authormergify[bot]2022-03-04 02:23:34 +0000
committerGitHub2022-03-04 02:23:34 +0000
commit3de61ead55662c919a0b9a47be105f883812b96c (patch)
tree6124ef4e361b130223fcf5a0960ecfaae7dd1ccf /core
parent271095622835df7b0025eb9fd55a99de9082dea2 (diff)
Issue errors on out-of-range extracts when width is known (#2428) (#2429)
* Issue errors on out-of-range extracts when width is known Firrtl will catch this later on, but better to error early if possible. * Test that errors are generated on OOB extracts when width is known (cherry picked from commit 462def429aa87becb544533880a3075a806c53e4) Co-authored-by: Andrew Waterman <andrew@sifive.com>
Diffstat (limited to 'core')
-rw-r--r--core/src/main/scala/chisel3/Bits.scala13
1 files changed, 13 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala
index 8a616d02..4133592f 100644
--- a/core/src/main/scala/chisel3/Bits.scala
+++ b/core/src/main/scala/chisel3/Bits.scala
@@ -107,6 +107,12 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
(((value >> castToInt(x, "Index")) & 1) == 1).asBool
}.getOrElse {
requireIsHardware(this, "bits to be indexed")
+
+ widthOption match {
+ case Some(w) if x >= w => Builder.error(s"High index $x is out of range [0, ${w - 1}]")
+ case _ =>
+ }
+
pushOp(DefPrim(sourceInfo, Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
}
}
@@ -160,6 +166,13 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
((value >> y) & ((BigInt(1) << w) - 1)).asUInt(w.W)
}.getOrElse {
requireIsHardware(this, "bits to be sliced")
+
+ widthOption match {
+ case Some(w) if y >= w => Builder.error(s"High and low indices $x and $y are both out of range [0, ${w - 1}]")
+ case Some(w) if x >= w => Builder.error(s"High index $x is out of range [0, ${w - 1}]")
+ case _ =>
+ }
+
pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y)))
}
}