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authorKevin Laeufer2021-08-30 16:06:59 -0700
committerGitHub2021-08-30 23:06:59 +0000
commit29665743acff120bc87ee997890d7f952317144e (patch)
treeba00667ca4899f5375529d5e73e4e9fbd97598dd /core
parent0a985f7d82d33b45bb35237bf3ca85d6f3936600 (diff)
SyncReadMem: fix bug with read(addr) and add some formal tests (#2092)
Diffstat (limited to 'core')
-rw-r--r--core/src/main/scala/chisel3/Mem.scala8
1 files changed, 7 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala
index 90525bfa..183620b6 100644
--- a/core/src/main/scala/chisel3/Mem.scala
+++ b/core/src/main/scala/chisel3/Mem.scala
@@ -213,8 +213,14 @@ sealed class SyncReadMem[T <: Data] private (t: T, n: BigInt, val readUnderWrite
var port: Option[T] = None
when (enable) {
a := addr
- port = Some(read(a))
+ port = Some(super.do_read(a))
}
port.get
}
+
+ /** @group SourceInfoTransformMacro*/
+ override def do_read(idx: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) =
+ do_read(addr = idx, enable = true.B)
+ // note: we implement do_read(addr) for SyncReadMem in terms of do_read(addr, en) in order to ensure that
+ // `mem.read(addr)` will always behave the same as `mem.read(addr, true.B)`
}