Add unit tests and fix for #2794 , add unit tests for #2773 (backport #2792) (#2834)

* Fixup and unit tests for D/I of IOs without explicit Input/Output (#2792)

(cherry picked from commit f24a624863f0fc460fd862238688ea8612ffdf5e)

# Conflicts:
#	core/src/main/scala/chisel3/Module.scala

* Resolve backport conflicts

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

1 files changed, 38 insertions, 29 deletions

diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 48c33083..e5c2a848 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -106,6 +106,38 @@ object Module extends SourceInfoDoc {
 
     module
   }
+
+  /**  Assign directionality on any IOs that are still Unspecified/Flipped
+    *
+    *  Chisel2 did not require explicit direction on nodes
+    *  (unspecified treated as output, and flip on nothing was input).
+    *  As of 3.6, chisel3 is now also using these semantics, so we need to make it work
+    *  even for chisel3 code.
+    *  This assigns the explicit directions required by both semantics on all Bundles.
+    * This recursively walks the tree, and assigns directions if no explicit
+    *   direction given by upper-levels (override Input / Output)
+    */
+  private[chisel3] def assignCompatDir(data: Data): Unit = {
+    data match {
+      case data: Element => data._assignCompatibilityExplicitDirection
+      case data: Aggregate =>
+        data.specifiedDirection match {
+          // Recurse into children to ensure explicit direction set somewhere
+          case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip =>
+            data match {
+              case record: Record =>
+                record.elementsIterator.foreach(assignCompatDir(_))
+              case vec: Vec[_] =>
+                vec.elementsIterator.foreach(assignCompatDir(_))
+                assignCompatDir(vec.sample_element) // This is used in fromChildren computation
+            }
+          case SpecifiedDirection.Input | SpecifiedDirection.Output =>
+          // forced assign, nothing to do
+          // The .bind algorithm will automatically assign the direction here.
+          // Thus, no implicit assignment is necessary.
+        }
+    }
+  }
 }
 
 /** Abstract base class for Modules, which behave much like Verilog modules.
@@ -382,6 +414,10 @@ package internal {
           new ClonePorts(proto.getChiselPorts :+ ("io" -> b._io.get): _*)
         case _ => new ClonePorts(proto.getChiselPorts: _*)
       }
+      // getChiselPorts (nor cloneTypeFull in general)
+      // does not recursively copy the right specifiedDirection,
+      // still need to fix it up here.
+      Module.assignCompatDir(clonePorts)
       clonePorts.bind(PortBinding(cloneParent))
       clonePorts.setAllParents(Some(cloneParent))
       cloneParent._portsRecord = clonePorts
@@ -691,35 +727,8 @@ package experimental {
       * io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.
       */
     protected def _bindIoInPlace(iodef: Data): Unit = {
-      // Compatibility code: Chisel2 did not require explicit direction on nodes
-      //   (unspecified treated as output, and flip on nothing was input).
-      // However, we are going to go back to Chisel2 semantics, so we need to make it work
-      //   even for chisel3 code.
-      // This assigns the explicit directions required by both semantics on all Bundles.
-      // This recursively walks the tree, and assigns directions if no explicit
-      //   direction given by upper-levels (override Input / Output)
-      def assignCompatDir(data: Data): Unit = {
-        data match {
-          case data: Element => data._assignCompatibilityExplicitDirection
-          case data: Aggregate =>
-            data.specifiedDirection match {
-              // Recurse into children to ensure explicit direction set somewhere
-              case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip =>
-                data match {
-                  case record: Record =>
-                    record.elementsIterator.foreach(assignCompatDir(_))
-                  case vec: Vec[_] =>
-                    vec.elementsIterator.foreach(assignCompatDir(_))
-                }
-              case SpecifiedDirection.Input | SpecifiedDirection.Output =>
-              // forced assign, nothing to do
-              // Note this is because Input and Output recurse down their types to align all fields to that SpecifiedDirection
-              // Thus, no implicit assigment is necessary.
-            }
-        }
-      }
-
-      assignCompatDir(iodef)
+      // Assign any signals (Chisel or chisel3) with Unspecified/Flipped directions to Output/Input
+      Module.assignCompatDir(iodef)
 
       iodef.bind(PortBinding(this))
       _ports += iodef