diff options
| author | Schuyler Eldridge | 2020-10-19 12:35:26 -0400 |
|---|---|---|
| committer | GitHub | 2020-10-19 16:35:26 +0000 |
| commit | ac641fb183e3a8866e6bd72123801cfb04a0c893 (patch) | |
| tree | 8a0839df9a42c47b7618ffcf944b989cd0dcc574 /core/src | |
| parent | baea2da820e9ebff5ba1b6ad9573a7cc33aaacbd (diff) | |
Enable Cat of Zero Element Vec (#1623)
* Return 0.U for asUInt of a zero-element Seq
Add a condition to SeqUtils.asUInt to have it return an unspecified
width 0.U when applied to an empty sequence. This enables the ability
to do a Cat of a zero-element sequence.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
* Test elaboration of Cat on zero-element Seq
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Diffstat (limited to 'core/src')
| -rw-r--r-- | core/src/main/scala/chisel3/SeqUtils.scala | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/SeqUtils.scala b/core/src/main/scala/chisel3/SeqUtils.scala index 64904e51..e263810a 100644 --- a/core/src/main/scala/chisel3/SeqUtils.scala +++ b/core/src/main/scala/chisel3/SeqUtils.scala @@ -15,12 +15,15 @@ private[chisel3] object SeqUtils { * in the sequence forms the most significant bits. * * Equivalent to r(n-1) ## ... ## r(1) ## r(0). + * @note This returns a `0.U` if applied to a zero-element `Vec`. */ def asUInt[T <: Bits](in: Seq[T]): UInt = macro SourceInfoTransform.inArg /** @group SourceInfoTransformMacros */ def do_asUInt[T <: Bits](in: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { - if (in.tail.isEmpty) { + if (in.isEmpty) { + 0.U + } else if (in.tail.isEmpty) { in.head.asUInt } else { val left = prefix("left") { |