diff options
| author | mergify[bot] | 2022-11-07 19:13:49 +0000 |
|---|---|---|
| committer | GitHub | 2022-11-07 19:13:49 +0000 |
| commit | 76ada881d077118384907f498576b3b338291ff6 (patch) | |
| tree | df425133f2395c25d3b21cd8ba438faa8320e5fb /core/src | |
| parent | 086c6806708d14ad5144ca064d4c644d0f62592d (diff) | |
Bugfix converter clearing flips (backport #2788) (#2832)
* Bugfix converter clearing flips (#2788)
* Bugfix: Output on Vec of bundle with mixed field orientations
* Bugfix OpaqueTypes clearing flips
(cherry picked from commit f05bff1a337589bafebd08783bb0f6a72092a95a)
# Conflicts:
# src/test/scala/chiselTests/Direction.scala
* Resolve backport conflicts
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'core/src')
| -rw-r--r-- | core/src/main/scala/chisel3/internal/firrtl/Converter.scala | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index fe95445c..f73e85d2 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -301,8 +301,11 @@ private[chisel3] object Converter { case d: SInt => fir.SIntType(convert(d.width)) case d: FixedPoint => fir.FixedType(convert(d.width), convert(d.binaryPoint)) case d: Interval => fir.IntervalType(d.range.lowerBound, d.range.upperBound, d.range.firrtlBinaryPoint) - case d: Analog => fir.AnalogType(convert(d.width)) - case d: Vec[_] => fir.VectorType(extractType(d.sample_element, clearDir, info), d.length) + case d: Analog => fir.AnalogType(convert(d.width)) + case d: Vec[_] => + val childClearDir = clearDir || + d.specifiedDirection == SpecifiedDirection.Input || d.specifiedDirection == SpecifiedDirection.Output + fir.VectorType(extractType(d.sample_element, childClearDir, info), d.length) case d: Record => { val childClearDir = clearDir || d.specifiedDirection == SpecifiedDirection.Input || d.specifiedDirection == SpecifiedDirection.Output @@ -316,7 +319,7 @@ private[chisel3] object Converter { if (!d.opaqueType) fir.BundleType(d.elements.toIndexedSeq.reverse.map { case (_, e) => eltField(e) }) else - extractType(d.elements.head._2, true, info) + extractType(d.elements.head._2, childClearDir, info) } } |