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authorJack Koenig2021-12-07 13:18:29 -0800
committerGitHub2021-12-07 21:18:29 +0000
commite85bfebb5d661de41f9ccac300fb48bf92840cfe (patch)
treec0209789b1226ad7e3ad14921831dca65b340d1d /core/src/main
parent12ed3fe9a780a9914b3f5727d921b4e419967549 (diff)
[docs] Remove body from minimizing output bits recipe (#2290)
Remove the body from the emitted Verilog. This was the original intent of the example, and it avoids an issue where Jekyll was not able to render the Markdown file due to Verilog concatenation looking like a variable escape.
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