diff options
| author | Aditya Naik | 2024-08-02 15:39:51 -0700 |
|---|---|---|
| committer | Aditya Naik | 2024-08-02 15:39:51 -0700 |
| commit | cf31062758d4d9722ac30f89fdfe7cc7c1d8cc74 (patch) | |
| tree | 2fe8eac756e3da2f2532e79b9f60081e313485a5 /core/src/main | |
| parent | 8947a5900e390c19524ab3013b33f0a8ec07ea43 (diff) | |
Update RawModule.scala
RawModule will require major reworking in the future
Diffstat (limited to 'core/src/main')
| -rw-r--r-- | core/src/main/scala/chisel3/RawModule.scala | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index bab1a5b1..cef0fa13 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -113,7 +113,7 @@ abstract class RawModule extends BaseModule { // // Other Internal Functions // - private var _firrtlPorts: Option[Seq[firrtl.Port]] = None + private var _firrtlPorts: Option[Seq[Port]] = None @deprecated("Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6", "Chisel 3.5") lazy val getPorts: Seq[Port] = _firrtlPorts.get @@ -167,7 +167,6 @@ abstract class RawModule extends BaseModule { // All suggestions are in, force names to every node. for (id <- getIds) { id match { - case id: ModuleClone[_] => id.setRefAndPortsRef(_namespace) // special handling case id: BaseModule => id.forceName(default = id.desiredName, _namespace) case id: MemBase[_] => id.forceName(default = "MEM", _namespace) // removed till macros are fixed @@ -192,11 +191,8 @@ abstract class RawModule extends BaseModule { } } // else, don't name unbound types } - id._onModuleClose } - closeUnboundIds(names) - val firrtlPorts = getModulePorts.map { port => // Special case Vec to make FIRRTL emit the direction of its // element. |