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authorJerry Zhao2020-09-09 14:43:17 -0700
committerGitHub2020-09-09 14:43:17 -0700
commit3b5fda0c604b393833769250ade9f7d13ca4e5e7 (patch)
treea6ec7f7afca2de99add817a12c5f49d530d473de /core/src/main
parenta2138cb11675d4eb17067c757c04b53590313c5d (diff)
Recursively generate one-hot multiplexers for aggregates (#1557)
Test all cases in ParameterizedOneHotTesters Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'core/src/main')
-rw-r--r--core/src/main/scala/chisel3/SeqUtils.scala13
1 files changed, 10 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/SeqUtils.scala b/core/src/main/scala/chisel3/SeqUtils.scala
index 9f068898..97bdc505 100644
--- a/core/src/main/scala/chisel3/SeqUtils.scala
+++ b/core/src/main/scala/chisel3/SeqUtils.scala
@@ -113,10 +113,17 @@ private[chisel3] object SeqUtils {
buildAndOrMultiplexor(sels.zip(inWidthMatched))
}
- case _: Aggregate =>
+ case agg: Aggregate =>
val allDefineWidth = in.forall { case (_, element) => element.widthOption.isDefined }
- if(allDefineWidth) {
- buildAndOrMultiplexor(in)
+ if (allDefineWidth) {
+ val out = Wire(agg)
+ val (sel, inData) = in.unzip
+ val inElts = inData.map(_.asInstanceOf[Aggregate].getElements)
+ // We want to iterate on the columns of inElts, so we transpose
+ out.getElements.zip(inElts.transpose).foreach { case (outElt, elts) =>
+ outElt := oneHotMux(sel.zip(elts))
+ }
+ out.asInstanceOf[T]
}
else {
throwException(s"Cannot Mux1H with aggregates with inferred widths")