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authormergify[bot]2022-11-08 17:27:07 +0000
committerGitHub2022-11-08 17:27:07 +0000
commitbfa9f7465e6069b1e624126f9e14245b69e7c0a9 (patch)
treee0aff2088021876ca9ab378fc2d321793937b791 /core/src/main/scala
parentf2ef3a8ee378a307661bd598cd44d4b895b9352e (diff)
Switch to using experimental trait for OpaqueTypes (backport #2783) (#2836)
* Switch to using experimental trait for OpaqueTypes (#2783) This makes it more clear that the feature is experimental. Users may still override the opaqueType method for more dynamic control over when instances of a given Record are OpaqueTypes or not, but they are discouraged from doing so. (cherry picked from commit 7525dc71ccc2050d8e4a68b38f3b76920ba693fc) * Fix cloneType in RecordSpec Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'core/src/main/scala')
-rw-r--r--core/src/main/scala/chisel3/Aggregate.scala20
-rw-r--r--core/src/main/scala/chisel3/experimental/OpaqueType.scala27
-rw-r--r--core/src/main/scala/chisel3/internal/firrtl/Converter.scala2
3 files changed, 34 insertions, 15 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala
index 16611277..f22f5e63 100644
--- a/core/src/main/scala/chisel3/Aggregate.scala
+++ b/core/src/main/scala/chisel3/Aggregate.scala
@@ -8,7 +8,7 @@ import chisel3.experimental.dataview.{isView, reifySingleData, InvalidViewExcept
import scala.collection.immutable.{SeqMap, VectorMap}
import scala.collection.mutable.{HashSet, LinkedHashMap}
import scala.language.experimental.macros
-import chisel3.experimental.{BaseModule, BundleLiteralException, ChiselEnum, EnumType, VecLiteralException}
+import chisel3.experimental.{BaseModule, BundleLiteralException, ChiselEnum, EnumType, OpaqueType, VecLiteralException}
import chisel3.internal._
import chisel3.internal.Builder.pushCommand
import chisel3.internal.firrtl._
@@ -881,23 +881,15 @@ trait VecLike[T <: Data] extends IndexedSeq[T] with HasId with SourceInfoDoc {
*/
abstract class Record(private[chisel3] implicit val compileOptions: CompileOptions) extends Aggregate {
- /** Indicates if this Record represents an "Opaque Type"
- *
- * Opaque types provide a mechanism for user-defined types
- * that do not impose any "boxing" overhead in the emitted FIRRTL and Verilog.
- * You can think about an opaque type Record as a box around
- * a single element that only exists at Chisel elaboration time.
- * Put another way, if opaqueType is overridden to true,
- * The Record may only contain a single element with an empty name
- * and there will be no `_` in the name for that element in the emitted Verilog.
- *
- * @see RecordSpec in Chisel's tests for example usage and expected output
- */
- def opaqueType: Boolean = false
+ private[chisel3] def _isOpaqueType: Boolean = this match {
+ case maybe: OpaqueType => maybe.opaqueType
+ case _ => false
+ }
// Doing this earlier than onModuleClose allows field names to be available for prefixing the names
// of hardware created when connecting to one of these elements
private def setElementRefs(): Unit = {
+ val opaqueType = this._isOpaqueType
// Since elements is a map, it is impossible for two elements to have the same
// identifier; however, Namespace sanitizes identifiers to make them legal for Firrtl/Verilog
// which can cause collisions
diff --git a/core/src/main/scala/chisel3/experimental/OpaqueType.scala b/core/src/main/scala/chisel3/experimental/OpaqueType.scala
new file mode 100644
index 00000000..e7a2a15d
--- /dev/null
+++ b/core/src/main/scala/chisel3/experimental/OpaqueType.scala
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package chisel3.experimental
+
+import chisel3._
+
+/** Indicates if this Record represents an "Opaque Type"
+ *
+ * Opaque types provide a mechanism for user-defined types
+ * that do not impose any "boxing" overhead in the emitted FIRRTL and Verilog.
+ * You can think about an opaque type Record as a box around
+ * a single element that only exists at Chisel elaboration time.
+ * Put another way, if this trait is mixed into a Record,
+ * the Record may only contain a single element with an empty name
+ * and there will be no `_` in the name for that element in the emitted Verilog.
+ *
+ * @see RecordSpec in Chisel's tests for example usage and expected output
+ */
+trait OpaqueType { self: Record =>
+
+ /** If set to true, indicates that this Record is an OpaqueType
+ *
+ * Users can override this if they need more dynamic control over the behavior for when
+ * instances of this type are considered opaque
+ */
+ def opaqueType: Boolean = true
+}
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index f73e85d2..3d6e0d79 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -316,7 +316,7 @@ private[chisel3] object Converter {
case (false, SpecifiedDirection.Flip | SpecifiedDirection.Input) =>
fir.Field(getRef(elt, info).name, fir.Flip, extractType(elt, false, info))
}
- if (!d.opaqueType)
+ if (!d._isOpaqueType)
fir.BundleType(d.elements.toIndexedSeq.reverse.map { case (_, e) => eltField(e) })
else
extractType(d.elements.head._2, childClearDir, info)