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| author | Schuyler Eldridge | 2020-08-12 12:10:44 -0400 |
|---|---|---|
| committer | GitHub | 2020-08-12 16:10:44 +0000 |
| commit | dbf4d546767d6983aec24dedf994651417ae2e50 (patch) | |
| tree | 38b122e0fea5364373ff468c0a4d0cb2310149c2 /core/src/main/scala/chisel3 | |
| parent | e0c805171ddb9707b0f9fe93e5d85ef9cdcab044 (diff) | |
Switch to HowToSerialize for Emission (#1405)
* Fix emit{Firrtl,Verilog} for CustomFileEmission
Change ChiselStage helper methods for emitting FIRRTL (emitFirrtl) and
Verilog (emitVerilog) to look for Circuit and Verilog annotations
instead of DeletedAnnotations. This is needed after migrating to the
CustomFileEmission mixin in FIRRTL where FIRRTL will no longer delete
emitter annotations.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Use CustomFileEmission for ChiselCircuitAnnotation
Removes the explicit chisel3.phases.Emitter and instead does emission
with a CustomFileEmission mixin to ChiselCircuitAnnotation. This then
prevents the need for passing around DeletedAnnotations. As a
consequence, I removed an unnecessary run of a second Converter in the
Driver.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Fix tests for use of CustomFileEmission trait
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
* Fixes for newer CustomFileEmission API
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'core/src/main/scala/chisel3')
0 files changed, 0 insertions, 0 deletions