diff options
| author | mergify[bot] | 2022-08-29 21:05:56 +0000 |
|---|---|---|
| committer | GitHub | 2022-08-29 21:05:56 +0000 |
| commit | 9f1484572e2e4185e87a9cfb03b253870636c12c (patch) | |
| tree | cc77f59b2a73082f412db7944c25c71ed54e8393 /core/src/main/scala/chisel3 | |
| parent | df5a95454ff0414d1d3ce16d06dbe27b152e3751 (diff) | |
Fix OpaqueSlot handling of contextual names (#2708) (#2712)
We need to ensure that contextual names stay contextual (ie. sensitive
to the module context which is important for naming ports).
(cherry picked from commit cee255216c4a1bb658a2d8ddc03d966ce7ffb877)
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'core/src/main/scala/chisel3')
| -rw-r--r-- | core/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index d177c859..ddad6b10 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -220,7 +220,7 @@ case class Slot(imm: Node, name: String) extends Arg { } case class OpaqueSlot(imm: Node) extends Arg { - override def contextualName(ctx: Component): String = imm.name + override def contextualName(ctx: Component): String = imm.contextualName(ctx) override def name: String = imm.name } |
