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authorAditya Naik2024-08-06 07:18:56 -0700
committerAditya Naik2024-08-06 07:18:56 -0700
commit276d7261208d640ea57a48cb592775c677726fb0 (patch)
treedd197a887c030bdab3513670c4ce5a690bb7e1c3 /core/src/main/scala/chisel3/package.scala
parent51864db8176662d134e1a260f92eafc83f9933d8 (diff)
Fix misc errors
Diffstat (limited to 'core/src/main/scala/chisel3/package.scala')
-rw-r--r--core/src/main/scala/chisel3/package.scala12
1 files changed, 11 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala
index be5fb7b5..203a499a 100644
--- a/core/src/main/scala/chisel3/package.scala
+++ b/core/src/main/scala/chisel3/package.scala
@@ -6,6 +6,7 @@ import java.util.{MissingFormatArgumentException, UnknownFormatConversionExcepti
import chisel3.experimental.VecLiterals._
import chisel3.experimental.BundleLiterals._
+import _root_.firrtl.annotations.{IsMember, Named, ReferenceTarget}
import scala.collection.mutable
import scala.annotation.tailrec
@@ -13,7 +14,7 @@ import scala.annotation.tailrec
/** This package contains the main chisel3 API.
*/
package object chisel3 {
- import internal.firrtl.{Port, Width}
+ import internal.firrtl.Port
import internal.Builder
import scala.language.implicitConversions
@@ -191,6 +192,15 @@ package object chisel3 {
def pathName: String
def parentPathName: String
def parentModName: String
+
+ /** Returns a FIRRTL Named that refers to this object in the elaborated hardware graph */
+ def toNamed: Named
+
+ /** Returns a FIRRTL IsMember that refers to this object in the elaborated hardware graph */
+ def toTarget: IsMember
+
+ /** Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph */
+ def toAbsoluteTarget: IsMember
}
@deprecated("MultiIOModule is now just Module", "Chisel 3.5")