diff options
| author | mergify[bot] | 2022-02-11 21:46:50 +0000 |
|---|---|---|
| committer | GitHub | 2022-02-11 21:46:50 +0000 |
| commit | be4feccad0d4fe487a0bea57cb44702c08831429 (patch) | |
| tree | dc1494da6275e23790020eba03652714ef7d533e /core/src/main/scala/chisel3/internal | |
| parent | 556ce6398e2f23d1f796d4626b4010f00726f4cd (diff) | |
Hierarchy API: make Mems lookupable (#2404) (#2410)
(cherry picked from commit 2a985ac376698a2e6300fbee13001d82d3e13989)
Co-authored-by: Deborah Soung <debs@sifive.com>
Diffstat (limited to 'core/src/main/scala/chisel3/internal')
| -rw-r--r-- | core/src/main/scala/chisel3/internal/Builder.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala index 247be57a..1ffe54ab 100644 --- a/core/src/main/scala/chisel3/internal/Builder.scala +++ b/core/src/main/scala/chisel3/internal/Builder.scala @@ -258,6 +258,7 @@ private[chisel3] trait HasId extends InstanceId { (p._component, this) match { case (Some(c), _) => refName(c) case (None, d: Data) if d.topBindingOpt == Some(CrossModuleBinding) => _ref.get.localName + case (None, _: MemBase[Data]) => _ref.get.localName case (None, _) => throwException(s"signalName/pathName should be called after circuit elaboration: $this, ${_parent}") } |