Working on Module.scala

2 files changed, 23 insertions, 0 deletions

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 5782a2f5..1c78f322 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -623,6 +623,27 @@ private[chisel3] object Builder extends LazyLogging {
       )
   }
 
+  def referenceUserModule: RawModule = {
+    currentModule match {
+      case Some(module: RawModule) => module
+      case _ =>
+        throwException(
+          "Error: Not in a RawModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox."
+          // A bare api call is, e.g. calling Wire() from the scala console).
+        )
+    }
+  }
+  def referenceUserContainer: BaseModule = {
+    currentModule match {
+      case Some(module: RawModule) => module
+      case _ =>
+        throwException(
+          "Error: Not in a RawModule. Likely cause: Missed Module() or Definition() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox."
+          // A bare api call is, e.g. calling Wire() from the scala console).
+        )
+    }
+  }
+
   def forcedUserModule: RawModule = currentModule match {
     case Some(module: RawModule) => module
     case _ =>
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 6789b041..de3d8716 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -325,6 +325,7 @@ case class DefMemPort[T <: Data](
   clock:      Arg)
     extends Definition
 @nowarn("msg=class Port") // delete when Port becomes private
+case class DefObject(id: HasId, className: String) extends Definition
 case class DefInstance(id: BaseModule, ports: Seq[Port]) extends Definition
 case class WhenBegin(pred: Arg) extends Command
 case class WhenEnd(firrtlDepth: Int, hasAlt: Boolean = false) extends Command
@@ -379,6 +380,7 @@ case class Circuit(
   ) = Circuit(name, components, annotations, renames, newAnnotations)
 
 }
+case class DefClass(id: Class[_], name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
 object Circuit
     extends scala.runtime.AbstractFunction4[String, Seq[Component], Seq[ChiselAnnotation], RenameMap, Circuit] {
   def unapply(c: Circuit): Option[(String, Seq[Component], Seq[ChiselAnnotation], RenameMap)] = {