Remove sourceinfo, compileoptions and other fixes

35 erros

4 files changed, 171 insertions, 251 deletions

diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala
index 82835052..46a2c134 100644
--- a/core/src/main/scala/chisel3/internal/BiConnect.scala
+++ b/core/src/main/scala/chisel3/internal/BiConnect.scala
@@ -7,8 +7,6 @@ import chisel3.experimental.{attach, Analog, BaseModule}
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.{Connect, Converter, DefInvalid}
 
-import scala.language.experimental.macros
-import chisel3.internal.sourceinfo._
 import _root_.firrtl.passes.CheckTypes
 
 /**
@@ -44,8 +42,8 @@ private[chisel3] object BiConnect {
     BiConnectException(s": Right Record missing field ($field).")
   def MismatchedException(left: String, right: String) =
     BiConnectException(s": Left ($left) and Right ($right) have different types.")
-  def AttachAlreadyBulkConnectedException(sourceInfo: SourceInfo) =
-    BiConnectException(sourceInfo.makeMessage(": Analog previously bulk connected at " + _))
+  def AttachAlreadyBulkConnectedException =
+    BiConnectException("Analog previously bulk connected")
   def DontCareCantBeSink =
     BiConnectException(": DontCare cannot be a connection sink (LHS)")
 
@@ -74,8 +72,6 @@ private[chisel3] object BiConnect {
     * - 4 is a special case of 2 turning into 3 for some subfields, when either side's subfield at `extends Bundle/Record` has `emitStrictConnects = false`
     */
   def connect(
-    sourceInfo:            SourceInfo,
-    connectCompileOptions: CompileOptions,
     left:                  Data,
     right:                 Data,
     context_mod:           BaseModule
@@ -84,22 +80,22 @@ private[chisel3] object BiConnect {
       // Handle element case (root case)
       case (left_a: Analog, right_a: Analog) =>
         try {
-          markAnalogConnected(sourceInfo, left_a, context_mod)
-          markAnalogConnected(sourceInfo, right_a, context_mod)
+          markAnalogConnected(left_a, context_mod)
+          markAnalogConnected(right_a, context_mod)
         } catch { // convert attach exceptions to BiConnectExceptions
           case attach.AttachException(message) => throw BiConnectException(message)
         }
-        attach.impl(Seq(left_a, right_a), context_mod)(sourceInfo)
+        attach.impl(Seq(left_a, right_a), context_mod)
       case (left_a: Analog, DontCare) =>
         try {
-          markAnalogConnected(sourceInfo, left_a, context_mod)
+          markAnalogConnected(left_a, context_mod)
         } catch { // convert attach exceptions to BiConnectExceptions
           case attach.AttachException(message) => throw BiConnectException(message)
         }
-        pushCommand(DefInvalid(sourceInfo, left_a.lref))
-      case (DontCare, right_a: Analog) => connect(sourceInfo, connectCompileOptions, right, left, context_mod)
+        pushCommand(DefInvalid(left_a.lref))
+      case (DontCare, right_a: Analog) => connect(right, left, context_mod)
       case (left_e: Element, right_e: Element) => {
-        elemConnect(sourceInfo, connectCompileOptions, left_e, right_e, context_mod)
+        elemConnect(left_e, right_e, context_mod)
         // TODO(twigg): Verify the element-level classes are connectable
       }
       // Handle Vec case
@@ -110,8 +106,7 @@ private[chisel3] object BiConnect {
 
         for (idx <- 0 until left_v.length) {
           try {
-            implicit val compileOptions = connectCompileOptions
-            connect(sourceInfo, connectCompileOptions, left_v(idx), right_v(idx), context_mod)
+            connect(left_v(idx), right_v(idx), context_mod)
           } catch {
             case BiConnectException(message) => throw BiConnectException(s"($idx)$message")
           }
@@ -121,8 +116,7 @@ private[chisel3] object BiConnect {
       case (left_v: Vec[Data @unchecked], DontCare) => {
         for (idx <- 0 until left_v.length) {
           try {
-            implicit val compileOptions = connectCompileOptions
-            connect(sourceInfo, connectCompileOptions, left_v(idx), right, context_mod)
+            connect(left_v(idx), right, context_mod)
           } catch {
             case BiConnectException(message) => throw BiConnectException(s"($idx)$message")
           }
@@ -132,8 +126,7 @@ private[chisel3] object BiConnect {
       case (DontCare, right_v: Vec[Data @unchecked]) => {
         for (idx <- 0 until right_v.length) {
           try {
-            implicit val compileOptions = connectCompileOptions
-            connect(sourceInfo, connectCompileOptions, left, right_v(idx), context_mod)
+            connect(left, right_v(idx), context_mod)
           } catch {
             case BiConnectException(message) => throw BiConnectException(s"($idx)$message")
           }
@@ -142,41 +135,32 @@ private[chisel3] object BiConnect {
       // Handle Records defined in Chisel._ code by emitting a FIRRTL bulk
       // connect when possible and a partial connect otherwise
       case pair @ (left_r: Record, right_r: Record) =>
-        val emitStrictConnects: Boolean =
-          left_r.compileOptions.emitStrictConnects && right_r.compileOptions.emitStrictConnects
+        val emitStrictConnects: Boolean = true
 
         // chisel3 <> is commutative but FIRRTL <- is not
         val flipConnection =
           !MonoConnect.canBeSink(left_r, context_mod) || !MonoConnect.canBeSource(right_r, context_mod)
         val (newLeft, newRight) = if (flipConnection) (right_r, left_r) else (left_r, right_r)
 
-        recordConnect(sourceInfo, connectCompileOptions, left_r, right_r, context_mod)
+        recordConnect(left_r, right_r, context_mod)
 
       // Handle Records connected to DontCare
       case (left_r: Record, DontCare) =>
-        if (!left_r.compileOptions.emitStrictConnects) {
-          left.legacyConnect(right)(sourceInfo)
-        } else {
-          // For each field in left, descend with right
-          for ((field, left_sub) <- left_r.elements) {
-            try {
-              connect(sourceInfo, connectCompileOptions, left_sub, right, context_mod)
-            } catch {
-              case BiConnectException(message) => throw BiConnectException(s".$field$message")
-            }
+        // For each field in left, descend with right
+        for ((field, left_sub) <- left_r.elements) {
+          try {
+            connect(left_sub, right, context_mod)
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s".$field$message")
           }
         }
       case (DontCare, right_r: Record) =>
-        if (!right_r.compileOptions.emitStrictConnects) {
-          left.legacyConnect(right)(sourceInfo)
-        } else {
-          // For each field in left, descend with right
-          for ((field, right_sub) <- right_r.elements) {
-            try {
-              connect(sourceInfo, connectCompileOptions, left, right_sub, context_mod)
-            } catch {
-              case BiConnectException(message) => throw BiConnectException(s".$field$message")
-            }
+        // For each field in left, descend with right
+        for ((field, right_sub) <- right_r.elements) {
+          try {
+            connect(left, right_sub, context_mod)
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s".$field$message")
           }
         }
 
@@ -187,8 +171,6 @@ private[chisel3] object BiConnect {
 
   // Do connection of two Records
   def recordConnect(
-    sourceInfo:            SourceInfo,
-    connectCompileOptions: CompileOptions,
     left_r:                Record,
     right_r:               Record,
     context_mod:           BaseModule
@@ -197,23 +179,17 @@ private[chisel3] object BiConnect {
 
     // For each field in left, descend with right.
     // Don't bother doing this check if we don't expect it to necessarily pass.
-    if (connectCompileOptions.connectFieldsMustMatch) {
-      for ((field, right_sub) <- right_r.elements) {
-        if (!left_r.elements.isDefinedAt(field)) {
-          throw MissingLeftFieldException(field)
-        }
+    for ((field, right_sub) <- right_r.elements) {
+      if (!left_r.elements.isDefinedAt(field)) {
+        throw MissingLeftFieldException(field)
       }
     }
     // For each field in left, descend with right
     for ((field, left_sub) <- left_r.elements) {
       try {
         right_r.elements.get(field) match {
-          case Some(right_sub) => connect(sourceInfo, connectCompileOptions, left_sub, right_sub, context_mod)
-          case None => {
-            if (connectCompileOptions.connectFieldsMustMatch) {
-              throw MissingRightFieldException(field)
-            }
-          }
+          case Some(right_sub) => connect(left_sub, right_sub, context_mod)
+          case None => throw MissingRightFieldException(field)
         }
       } catch {
         case BiConnectException(message) => throw BiConnectException(s".$field$message")
@@ -235,22 +211,18 @@ private[chisel3] object BiConnect {
   private[chisel3] def canBulkConnectAggregates(
     sink:                  Aggregate,
     source:                Aggregate,
-    sourceInfo:            SourceInfo,
-    connectCompileOptions: CompileOptions,
     context_mod:           BaseModule
   ): Boolean = {
 
     // check that the aggregates have the same types
     def typeCheck = CheckTypes.validConnect(
-      Converter.extractType(sink, sourceInfo),
-      Converter.extractType(source, sourceInfo)
+      Converter.extractType(sink),
+      Converter.extractType(source)
     )
 
     // check records live in appropriate contexts
     def contextCheck =
       MonoConnect.aggregateConnectContextCheck(
-        sourceInfo,
-        connectCompileOptions,
         sink,
         source,
         context_mod
@@ -276,33 +248,31 @@ private[chisel3] object BiConnect {
 
   // These functions (finally) issue the connection operation
   // Issue with right as sink, left as source
-  private def issueConnectL2R(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+  private def issueConnectL2R(left: Element, right: Element): Unit = {
     // Source and sink are ambiguous in the case of a Bi/Bulk Connect (<>).
     // If either is a DontCareBinding, just issue a DefInvalid for the other,
     //  otherwise, issue a Connect.
     (left.topBinding, right.topBinding) match {
-      case (lb: DontCareBinding, _) => pushCommand(DefInvalid(sourceInfo, right.lref))
-      case (_, rb: DontCareBinding) => pushCommand(DefInvalid(sourceInfo, left.lref))
-      case (_, _) => pushCommand(Connect(sourceInfo, right.lref, left.ref))
+      case (lb: DontCareBinding, _) => pushCommand(DefInvalid(right.lref))
+      case (_, rb: DontCareBinding) => pushCommand(DefInvalid(left.lref))
+      case (_, _) => pushCommand(Connect(right.lref, left.ref))
     }
   }
   // Issue with left as sink, right as source
-  private def issueConnectR2L(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+  private def issueConnectR2L(left: Element, right: Element): Unit = {
     // Source and sink are ambiguous in the case of a Bi/Bulk Connect (<>).
     // If either is a DontCareBinding, just issue a DefInvalid for the other,
     //  otherwise, issue a Connect.
     (left.topBinding, right.topBinding) match {
-      case (lb: DontCareBinding, _) => pushCommand(DefInvalid(sourceInfo, right.lref))
-      case (_, rb: DontCareBinding) => pushCommand(DefInvalid(sourceInfo, left.lref))
-      case (_, _) => pushCommand(Connect(sourceInfo, left.lref, right.ref))
+      case (lb: DontCareBinding, _) => pushCommand(DefInvalid(right.lref))
+      case (_, rb: DontCareBinding) => pushCommand(DefInvalid(left.lref))
+      case (_, _) => pushCommand(Connect(left.lref, right.ref))
     }
   }
 
   // This function checks if element-level connection operation allowed.
   // Then it either issues it or throws the appropriate exception.
   def elemConnect(
-    implicit sourceInfo:   SourceInfo,
-    connectCompileOptions: CompileOptions,
     _left:                 Element,
     _right:                Element,
     context_mod:           BaseModule
@@ -369,13 +339,7 @@ private[chisel3] object BiConnect {
 
         case (Input, Input)   => throw BothDriversException
         case (Output, Output) => throw BothDriversException
-        case (Internal, Internal) => {
-          if (connectCompileOptions.dontAssumeDirectionality) {
-            throw UnknownDriverException
-          } else {
-            issueConnectR2L(left, right)
-          }
-        }
+        case (Internal, Internal) => throw UnknownDriverException
       }
     }
 
@@ -391,18 +355,8 @@ private[chisel3] object BiConnect {
 
         case (Input, Input)   => throw NeitherDriverException
         case (Output, Output) => throw BothDriversException
-        case (_, Internal) =>
-          if (connectCompileOptions.dontAssumeDirectionality) {
-            throw UnknownRelationException
-          } else {
-            issueConnectR2L(left, right)
-          }
-        case (Internal, _) =>
-          if (connectCompileOptions.dontAssumeDirectionality) {
-            throw UnknownRelationException
-          } else {
-            issueConnectR2L(left, right)
-          }
+        case (_, Internal) => throw UnknownRelationException
+        case (Internal, _) => throw UnknownRelationException
       }
     }
 
@@ -412,12 +366,10 @@ private[chisel3] object BiConnect {
   }
 
   // This function checks if analog element-level attaching is allowed, then marks the Analog as connected
-  def markAnalogConnected(implicit sourceInfo: SourceInfo, analog: Analog, contextModule: BaseModule): Unit = {
+  def markAnalogConnected(analog: Analog, contextModule: BaseModule): Unit = {
     analog.biConnectLocs.get(contextModule) match {
-      case Some(sl) => throw AttachAlreadyBulkConnectedException(sl)
+      case Some(sl) => throw AttachAlreadyBulkConnectedException
       case None     => // Do nothing
     }
-    // Mark bulk connected
-    analog.biConnectLocs(contextModule) = sourceInfo
   }
 }
diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala
index 1389d508..51db0fe7 100644
--- a/core/src/main/scala/chisel3/internal/MonoConnect.scala
+++ b/core/src/main/scala/chisel3/internal/MonoConnect.scala
@@ -7,7 +7,6 @@ import chisel3.experimental.{Analog, BaseModule, UnsafeEnum}
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.{Connect, Converter, DefInvalid}
 
-import chisel3.internal.sourceinfo.SourceInfo
 import _root_.firrtl.passes.CheckTypes
 import scala.annotation.tailrec
 
@@ -90,8 +89,6 @@ private[chisel3] object MonoConnect {
     * This gives the user a 'path' to where in the connections things went wrong.
     */
   def connect(
-    sourceInfo:            SourceInfo,
-    connectCompileOptions: CompileOptions,
     sink:                  Data,
     source:                Data,
     context_mod:           BaseModule
@@ -100,35 +97,34 @@ private[chisel3] object MonoConnect {
 
       // Handle legal element cases, note (Bool, Bool) is caught by the first two, as Bool is a UInt
       case (sink_e: Bool, source_e: UInt) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: UInt, source_e: Bool) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: UInt, source_e: UInt) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: SInt, source_e: SInt) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: Clock, source_e: Clock) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: AsyncReset, source_e: AsyncReset) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: ResetType, source_e: Reset) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: Reset, source_e: ResetType) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: EnumType, source_e: UnsafeEnum) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: EnumType, source_e: EnumType) if sink_e.typeEquivalent(source_e) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
       case (sink_e: UnsafeEnum, source_e: UInt) =>
-        elemConnect(sourceInfo, connectCompileOptions, sink_e, source_e, context_mod)
+        elemConnect(sink_e, source_e, context_mod)
 
       // Handle Vec case
       case (sink_v: Vec[Data @unchecked], source_v: Vec[Data @unchecked]) =>
         if (sink_v.length != source_v.length) { throw MismatchedVecException }
         for (idx <- 0 until sink_v.length) {
           try {
-            implicit val compileOptions = connectCompileOptions
-            connect(sourceInfo, connectCompileOptions, sink_v(idx), source_v(idx), context_mod)
+            connect(sink_v(idx), source_v(idx), context_mod)
           } catch {
             case MonoConnectException(message) => throw MonoConnectException(s"($idx)$message")
           }
@@ -137,8 +133,7 @@ private[chisel3] object MonoConnect {
       case (sink_v: Vec[Data @unchecked], DontCare) =>
         for (idx <- 0 until sink_v.length) {
           try {
-            implicit val compileOptions = connectCompileOptions
-            connect(sourceInfo, connectCompileOptions, sink_v(idx), source, context_mod)
+            connect(sink_v(idx), source, context_mod)
           } catch {
             case MonoConnectException(message) => throw MonoConnectException(s"($idx)$message")
           }
@@ -150,11 +145,9 @@ private[chisel3] object MonoConnect {
         for ((field, sink_sub) <- sink_r.elements) {
           try {
             source_r.elements.get(field) match {
-              case Some(source_sub) => connect(sourceInfo, connectCompileOptions, sink_sub, source_sub, context_mod)
+              case Some(source_sub) => connect(sink_sub, source_sub, context_mod)
               case None => {
-                if (connectCompileOptions.connectFieldsMustMatch) {
-                  throw MissingFieldException(field)
-                }
+                throw MissingFieldException(field)
               }
             }
           } catch {
@@ -166,7 +159,7 @@ private[chisel3] object MonoConnect {
         // For each field, descend with right
         for ((field, sink_sub) <- sink_r.elements) {
           try {
-            connect(sourceInfo, connectCompileOptions, sink_sub, source, context_mod)
+            connect(sink_sub, source, context_mod)
           } catch {
             case MonoConnectException(message) => throw MonoConnectException(s".$field$message")
           }
@@ -174,7 +167,7 @@ private[chisel3] object MonoConnect {
 
       // Source is DontCare - it may be connected to anything. It generates a defInvalid for the sink.
       case (sink: Element, DontCare) =>
-        pushCommand(DefInvalid(sourceInfo, sink.lref))
+        pushCommand(DefInvalid(sink.lref))
       // DontCare as a sink is illegal.
       case (DontCare, _) => throw DontCareCantBeSink
       // Analog is illegal in mono connections.
@@ -193,8 +186,6 @@ private[chisel3] object MonoConnect {
     * @return whether the source and sink exist in an appropriate context to be connected
     */
   private[chisel3] def aggregateConnectContextCheck(
-    implicit sourceInfo:   SourceInfo,
-    connectCompileOptions: CompileOptions,
     sink:                  Aggregate,
     source:                Aggregate,
     context_mod:           BaseModule
@@ -241,11 +232,10 @@ private[chisel3] object MonoConnect {
         case _                => false
       }
       // Thus, right node better be a port node and thus have a direction
-      if (!source_is_port) { !connectCompileOptions.dontAssumeDirectionality }
+      if (!source_is_port) { false }
       else if (sinkCanBeInput) {
-        if (source.direction == Output) {
-          !connectCompileOptions.dontTryConnectionsSwapped
-        } else { false }
+        if (source.direction == Output) { true }
+        else { false }
       } else { true }
     }
 
@@ -266,7 +256,7 @@ private[chisel3] object MonoConnect {
     //   Note: This includes case when sink and source in same module but in parent
     else if ((sink_parent == context_mod) && (source_parent == context_mod)) {
       // Thus both nodes must be ports and have a direction
-      if (!source_is_port) { !connectCompileOptions.dontAssumeDirectionality }
+      if (!source_is_port) { false }
       else if (sink_is_port) {
         // NOTE: Workaround for bulk connecting non-agnostified FIRRTL ports
         // See: https://github.com/freechipsproject/firrtl/issues/1703
@@ -323,13 +313,11 @@ private[chisel3] object MonoConnect {
   private[chisel3] def canBulkConnectAggregates(
     sink:                  Aggregate,
     source:                Aggregate,
-    sourceInfo:            SourceInfo,
-    connectCompileOptions: CompileOptions,
     context_mod:           BaseModule
   ): Boolean = {
     // Assuming we're using a <>, check if a bulk connect is valid in that case
     def biConnectCheck =
-      BiConnect.canBulkConnectAggregates(sink, source, sourceInfo, connectCompileOptions, context_mod)
+      BiConnect.canBulkConnectAggregates(sink, source, context_mod)
 
     // Check that the Aggregate can be driven (not bidirectional or an input) to match Chisel semantics
     def sinkCanBeDrivenCheck: Boolean =
@@ -339,20 +327,18 @@ private[chisel3] object MonoConnect {
   }
 
   // This function (finally) issues the connection operation
-  private def issueConnect(sink: Element, source: Element)(implicit sourceInfo: SourceInfo): Unit = {
+  private def issueConnect(sink: Element, source: Element): Unit = {
     // If the source is a DontCare, generate a DefInvalid for the sink,
     //  otherwise, issue a Connect.
     source.topBinding match {
-      case b: DontCareBinding => pushCommand(DefInvalid(sourceInfo, sink.lref))
-      case _ => pushCommand(Connect(sourceInfo, sink.lref, source.ref))
+      case b: DontCareBinding => pushCommand(DefInvalid(sink.lref))
+      case _ => pushCommand(Connect(sink.lref, source.ref))
     }
   }
 
   // This function checks if element-level connection operation allowed.
   // Then it either issues it or throws the appropriate exception.
   def elemConnect(
-    implicit sourceInfo:   SourceInfo,
-    connectCompileOptions: CompileOptions,
     sink:                 Element,
     source:               Element,
     context_mod:           BaseModule
@@ -398,15 +384,9 @@ private[chisel3] object MonoConnect {
         case (Internal, Input)  => issueConnect(sink, source)
         case (Output, Output)   => issueConnect(sink, source)
         case (Output, Input)    => issueConnect(sink, source)
-        case (_, Internal) => {
-          if (!(connectCompileOptions.dontAssumeDirectionality)) {
-            issueConnect(sink, source)
-          } else {
-            throw UnreadableSourceException(sink, source)
-          }
-        }
-        case (Input, Output) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink)
-        case (Input, _)                                                              => throw UnwritableSinkException(sink, source)
+        case (_, Internal) => throw UnreadableSourceException(sink, source)
+        case (Input, Output)  => issueConnect(source, sink)
+        case (Input, _) => throw UnwritableSinkException(sink, source)
       }
     }
 
@@ -434,11 +414,7 @@ private[chisel3] object MonoConnect {
         case (Input, Output) => issueConnect(sink, source)
         case (Output, _)     => throw UnwritableSinkException(sink, source)
         case (_, Internal) => {
-          if (!(connectCompileOptions.dontAssumeDirectionality)) {
-            issueConnect(sink, source)
-          } else {
-            throw UnreadableSourceException(sink, source)
-          }
+          issueConnect(sink, source)
         }
         case (Internal, _) => throw UnwritableSinkException(sink, source)
       }
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index 93676fef..3c4a01b2 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -3,7 +3,6 @@
 package chisel3.internal.firrtl
 import chisel3._
 import chisel3.experimental._
-import chisel3.internal.sourceinfo.{NoSourceInfo, SourceInfo, SourceLine, UnlocatableSourceInfo}
 import firrtl.{ir => fir}
 import chisel3.internal.{castToInt, throwException, HasId}
 
@@ -32,22 +31,19 @@ private[chisel3] object Converter {
     throwException(fullMsg)
   }
 
-  def getRef(id: HasId, sourceInfo: SourceInfo): Arg =
+  def getRef(id: HasId): Arg =
     id.getOptionRef.getOrElse {
       val module = id._parent.map(m => s" '$id' was defined in module '$m'.").getOrElse("")
-      val loc = sourceInfo.makeMessage(" " + _)
+      val loc = ""
       reportInternalError(s"Could not get ref for '$id'$loc!$module")
     }
 
-  private def clonedModuleIOError(mod: BaseModule, name: String, sourceInfo: SourceInfo): Nothing = {
-    val loc = sourceInfo.makeMessage(" " + _)
+  private def clonedModuleIOError(mod: BaseModule, name: String): Nothing = {
+    val loc = ""
     reportInternalError(s"Trying to convert a cloned IO of $mod inside of $mod itself$loc!")
   }
 
-  def convert(info: SourceInfo): fir.Info = info match {
-    case _: NoSourceInfo => fir.NoInfo
-    case SourceLine(fn, line, col) => fir.FileInfo(fir.StringLit(s"$fn $line:$col"))
-  }
+  // def convert(info: SourceInfo): fir.Info = fir.NoInfo
 
   def convert(op: PrimOp): fir.PrimOp = firrtl.PrimOps.fromString(op.name)
 
@@ -61,24 +57,24 @@ private[chisel3] object Converter {
   // TODO
   //   * Memoize?
   //   * Move into the Chisel IR?
-  def convert(arg: Arg, ctx: Component, info: SourceInfo): fir.Expression = arg match {
+  def convert(arg: Arg, ctx: Component): fir.Expression = arg match {
     case Node(id) =>
-      convert(getRef(id, info), ctx, info)
+      convert(getRef(id), ctx)
     case Ref(name) =>
       fir.Reference(name, fir.UnknownType)
     case Slot(imm, name) =>
-      fir.SubField(convert(imm, ctx, info), name, fir.UnknownType)
+      fir.SubField(convert(imm, ctx), name, fir.UnknownType)
     case OpaqueSlot(imm) =>
-      convert(imm, ctx, info)
+      convert(imm, ctx)
     case Index(imm, ILit(idx)) =>
-      fir.SubIndex(convert(imm, ctx, info), castToInt(idx, "Index"), fir.UnknownType)
+      fir.SubIndex(convert(imm, ctx), castToInt(idx, "Index"), fir.UnknownType)
     case Index(imm, value) =>
-      fir.SubAccess(convert(imm, ctx, info), convert(value, ctx, info), fir.UnknownType)
+      fir.SubAccess(convert(imm, ctx), convert(value, ctx), fir.UnknownType)
     case ModuleIO(mod, name) =>
       if (mod eq ctx.id) fir.Reference(name, fir.UnknownType)
-      else fir.SubField(fir.Reference(getRef(mod, info).name, fir.UnknownType), name, fir.UnknownType)
+      else fir.SubField(fir.Reference(getRef(mod).name, fir.UnknownType), name, fir.UnknownType)
     case ModuleCloneIO(mod, name) =>
-      if (mod eq ctx.id) clonedModuleIOError(mod, name, info)
+      if (mod eq ctx.id) clonedModuleIOError(mod, name)
       else fir.Reference(name)
     case u @ ULit(n, UnknownWidth()) =>
       fir.UIntLiteral(n, fir.IntWidth(u.minWidth))
@@ -87,7 +83,7 @@ private[chisel3] object Converter {
     case slit @ SLit(n, w) =>
       fir.SIntLiteral(n, convert(w))
       val unsigned = if (n < 0) (BigInt(1) << slit.width.get) + n else n
-      val uint = convert(ULit(unsigned, slit.width), ctx, info)
+      val uint = convert(ULit(unsigned, slit.width), ctx)
       fir.DoPrim(firrtl.PrimOps.AsSInt, Seq(uint), Seq.empty, fir.UnknownType)
     // TODO Simplify
     case lit: ILit =>
@@ -100,7 +96,7 @@ private[chisel3] object Converter {
       val consts = e.args.collect { case ILit(i) => i }
       val args = e.args.flatMap {
         case _: ILit => None
-        case other => Some(convert(other, ctx, e.sourceInfo))
+        case other => Some(convert(other, ctx, fir.NoInfo))
       }
       val expr = e.op.name match {
         case "mux" =>
@@ -109,86 +105,87 @@ private[chisel3] object Converter {
         case _ =>
           fir.DoPrim(convert(e.op), args, consts, fir.UnknownType)
       }
-      Some(fir.DefNode(convert(e.sourceInfo), e.name, expr))
-    case e @ DefWire(info, id) =>
-      Some(fir.DefWire(convert(info), e.name, extractType(id, info)))
-    case e @ DefReg(info, id, clock) =>
+      Some(fir.DefNode(fir.NoInfo, e.name, expr))
+    case e @ DefWire(id) =>
+      Some(fir.DefWire(fir.NoInfo, e.name, extractType(id)))
+    case e @ DefReg(id, clock) =>
       Some(
         fir.DefRegister(
-          convert(info),
+          fir.NoInfo,
           e.name,
-          extractType(id, info),
-          convert(clock, ctx, info),
+          extractType(id),
+          convert(clock, ctx),
           firrtl.Utils.zero,
-          convert(getRef(id, info), ctx, info)
+          convert(getRef(id), ctx)
         )
       )
-    case e @ DefRegInit(info, id, clock, reset, init) =>
+    case e @ DefRegInit(id, clock, reset, init) =>
       Some(
         fir.DefRegister(
-          convert(info),
+          fir.NoInfo,
           e.name,
-          extractType(id, info),
-          convert(clock, ctx, info),
-          convert(reset, ctx, info),
-          convert(init, ctx, info)
+          extractType(id),
+          convert(clock, ctx),
+          convert(reset, ctx),
+          convert(init, ctx)
         )
       )
-    case e @ DefMemory(info, id, t, size) =>
-      Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info), size, false))
-    case e @ DefSeqMemory(info, id, t, size, ruw) =>
-      Some(firrtl.CDefMemory(convert(info), e.name, extractType(t, info), size, true, ruw))
+    case e @ DefMemory(id, t, size) =>
+      Some(firrtl.CDefMemory(fir.NoInfo, e.name, extractType(t), size, false))
+    case e @ DefSeqMemory(id, t, size, ruw) =>
+      Some(firrtl.CDefMemory(fir.NoInfo, e.name, extractType(t), size, true, ruw))
     case e: DefMemPort[_] =>
-      val info = e.sourceInfo
+      val info = fir.NoInfo
       Some(
         firrtl.CDefMPort(
-          convert(e.sourceInfo),
+          fir.NoInfo,
           e.name,
           fir.UnknownType,
           e.source.fullName(ctx),
-          Seq(convert(e.index, ctx, info), convert(e.clock, ctx, info)),
+          Seq(convert(e.index, ctx), convert(e.clock, ctx)),
           convert(e.dir)
         )
       )
-    case Connect(info, loc, exp) =>
-      Some(fir.Connect(convert(info), convert(loc, ctx, info), convert(exp, ctx, info)))
-    case BulkConnect(info, loc, exp) =>
-      Some(fir.PartialConnect(convert(info), convert(loc, ctx, info), convert(exp, ctx, info)))
-    case Attach(info, locs) =>
-      Some(fir.Attach(convert(info), locs.map(l => convert(l, ctx, info))))
-    case DefInvalid(info, arg) =>
-      Some(fir.IsInvalid(convert(info), convert(arg, ctx, info)))
-    case e @ DefInstance(info, id, _) =>
-      Some(fir.DefInstance(convert(info), e.name, id.name))
-    case e @ Printf(_, info, clock, pable) =>
+    case Connect(loc, exp) =>
+      Some(fir.Connect(fir.NoInfo, convert(loc, ctx), convert(exp, ctx)))
+    case BulkConnect(loc, exp) =>
+      Some(fir.PartialConnect(fir.NoInfo, convert(loc, ctx), convert(exp, ctx)))
+    case Attach(locs) =>
+      Some(fir.Attach(fir.NoInfo, locs.map(l => convert(l, ctx))))
+    case DefInvalid(arg) =>
+      Some(fir.IsInvalid(fir.NoInfo, convert(arg, ctx)))
+    case e @ DefInstance(id, _) =>
+      Some(fir.DefInstance(fir.NoInfo, e.name, id.name))
+    case e @ Printf(_, clock, pable) =>
       val (fmt, args) = unpack(pable, ctx)
       Some(
         fir.Print(
-          convert(info),
+          fir.NoInfo,
           fir.StringLit(fmt),
-          args.map(a => convert(a, ctx, info)),
-          convert(clock, ctx, info),
+          args.map(a => convert(a, ctx)),
+          convert(clock, ctx),
           firrtl.Utils.one,
           e.name
         )
       )
-    case e @ Verification(_, op, info, clk, pred, msg) =>
+    case e @ Verification(_, op, clk, pred, msg) =>
       val firOp = op match {
         case Formal.Assert => fir.Formal.Assert
         case Formal.Assume => fir.Formal.Assume
         case Formal.Cover  => fir.Formal.Cover
       }
-      Some(
-        fir.Verification(
-          firOp,
-          convert(info),
-          convert(clk, ctx, info),
-          convert(pred, ctx, info),
-          firrtl.Utils.one,
-          fir.StringLit(msg),
-          e.name
-        )
-      )
+      None
+      // Some(
+      //   fir.Verification(
+      //     firOp,
+      //     fir.NoInfo,
+      //     convert(clk, ctx),
+      //     convert(pred, ctx),
+      //     firrtl.Utils.one,
+      //     fir.StringLit(msg),
+      //     e.name
+      //   )
+      // )
     case _ => None
   }
 
@@ -236,12 +233,12 @@ private[chisel3] object Converter {
         // Please see WhenFrame for more details
         case None =>
           cmd match {
-            case WhenBegin(info, pred) =>
-              val when = fir.Conditionally(convert(info), convert(pred, ctx, info), fir.EmptyStmt, fir.EmptyStmt)
+            case WhenBegin(pred) =>
+              val when = fir.Conditionally(fir.NoInfo, convert(pred, ctx), fir.EmptyStmt, fir.EmptyStmt)
               val frame = WhenFrame(when, stmts, false)
               stmts = new VectorBuilder[fir.Statement]
               scope = frame :: scope
-            case WhenEnd(info, depth, _) =>
+            case WhenEnd(depth, _) =>
               val frame = scope.head
               val when =
                 if (frame.alt) frame.when.copy(alt = fir.Block(stmts.result()))
@@ -258,19 +255,19 @@ private[chisel3] object Converter {
                   // If we're nested we need to add more WhenEnds to ensure each When scope gets
                   // properly closed
                   if (depth > 0) {
-                    nextCmd = WhenEnd(info, depth - 1, false)
+                    nextCmd = WhenEnd(depth - 1, false)
                   }
                   stmts = frame.outer
                   stmts += when
                   scope = scope.tail
               }
-            case OtherwiseEnd(info, depth) =>
+            case OtherwiseEnd(depth) =>
               val frame = scope.head
               val when = frame.when.copy(alt = fir.Block(stmts.result()))
               // TODO For some reason depth == 1 indicates the last closing otherwise whereas
               //  depth == 0 indicates last closing when
               if (depth > 1) {
-                nextCmd = OtherwiseEnd(info, depth - 1)
+                nextCmd = OtherwiseEnd(depth - 1)
               }
               stmts = frame.outer
               stmts += when
@@ -298,9 +295,9 @@ private[chisel3] object Converter {
     case d => d.specifiedDirection
   }
 
-  def extractType(data: Data, info: SourceInfo): fir.Type = extractType(data, false, info)
+  def extractType(data: Data): fir.Type = extractType(data, false)
 
-  def extractType(data: Data, clearDir: Boolean, info: SourceInfo): fir.Type = data match {
+  def extractType(data: Data, clearDir: Boolean): fir.Type = data match {
     case _: Clock      => fir.ClockType
     case _: AsyncReset => fir.AsyncResetType
     case _: ResetType  => fir.ResetType
@@ -311,21 +308,21 @@ private[chisel3] object Converter {
     case d: Vec[_] =>
       val childClearDir = clearDir ||
         d.specifiedDirection == SpecifiedDirection.Input || d.specifiedDirection == SpecifiedDirection.Output
-      fir.VectorType(extractType(d.sample_element, childClearDir, info), d.length)
+      fir.VectorType(extractType(d.sample_element, childClearDir), d.length)
     case d: Record => {
       val childClearDir = clearDir ||
         d.specifiedDirection == SpecifiedDirection.Input || d.specifiedDirection == SpecifiedDirection.Output
       def eltField(elt: Data): fir.Field = (childClearDir, firrtlUserDirOf(elt)) match {
-        case (true, _) => fir.Field(getRef(elt, info).name, fir.Default, extractType(elt, true, info))
+        case (true, _) => fir.Field(getRef(elt).name, fir.Default, extractType(elt, true))
         case (false, SpecifiedDirection.Unspecified | SpecifiedDirection.Output) =>
-          fir.Field(getRef(elt, info).name, fir.Default, extractType(elt, false, info))
+          fir.Field(getRef(elt).name, fir.Default, extractType(elt, false))
         case (false, SpecifiedDirection.Flip | SpecifiedDirection.Input) =>
-          fir.Field(getRef(elt, info).name, fir.Flip, extractType(elt, false, info))
+          fir.Field(getRef(elt).name, fir.Flip, extractType(elt, false))
       }
       if (!d._isOpaqueType)
         fir.BundleType(d.elements.toIndexedSeq.reverse.map { case (_, e) => eltField(e) })
       else
-        extractType(d.elements.head._2, childClearDir, info)
+        extractType(d.elements.head._2, childClearDir)
     }
   }
 
@@ -339,9 +336,9 @@ private[chisel3] object Converter {
       case SpecifiedDirection.Input | SpecifiedDirection.Output     => true
       case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => false
     }
-    val info = UnlocatableSourceInfo // Unfortunately there is no source locator for ports ATM
-    val tpe = extractType(port.id, clearDir, info)
-    fir.Port(fir.NoInfo, getRef(port.id, info).name, dir, tpe)
+
+    val tpe = extractType(port.id, clearDir)
+    fir.Port(fir.NoInfo, getRef(port.id).name, dir, tpe)
   }
 
   def convert(component: Component): fir.DefModule = component match {
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 0e0ebef2..6f993847 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -5,7 +5,6 @@ package chisel3.internal.firrtl
 import firrtl.{ir => fir}
 import chisel3._
 import chisel3.internal._
-import chisel3.internal.sourceinfo.SourceInfo
 import chisel3.experimental._
 import _root_.firrtl.{ir => firrtlir}
 import _root_.firrtl.{PrimOps, RenameMap}
@@ -294,28 +293,24 @@ object MemPortDirection {
   object INFER extends MemPortDirection("infer")
 }
 
-abstract class Command {
-  def sourceInfo: SourceInfo
-}
+abstract class Command
 abstract class Definition extends Command {
   def id: HasId
   def name: String = id.getRef.name
 }
-case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
-case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
-case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
-case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
-case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
-case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
+case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
+case class DefInvalid(arg: Arg) extends Command
+case class DefWire(id: Data) extends Definition
+case class DefReg(id: Data, clock: Arg) extends Definition
+case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
+case class DefMemory(id: HasId, t: Data, size: BigInt) extends Definition
 case class DefSeqMemory(
-  sourceInfo:     SourceInfo,
   id:             HasId,
   t:              Data,
   size:           BigInt,
   readUnderWrite: fir.ReadUnderWrite.Value)
     extends Definition
 case class DefMemPort[T <: Data](
-  sourceInfo: SourceInfo,
   id:         T,
   source:     Node,
   dir:        MemPortDirection,
@@ -323,18 +318,18 @@ case class DefMemPort[T <: Data](
   clock:      Arg)
     extends Definition
 @nowarn("msg=class Port") // delete when Port becomes private
-case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition
-case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command
-case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command
-case class AltBegin(sourceInfo: SourceInfo) extends Command
-case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command
-case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
-case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
-case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
-case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
+case class DefInstance(id: BaseModule, ports: Seq[Port]) extends Definition
+case class WhenBegin(pred: Arg) extends Command
+case class WhenEnd(firrtlDepth: Int, hasAlt: Boolean = false) extends Command
+case class AltBegin() extends Command
+case class OtherwiseEnd(firrtlDepth: Int) extends Command
+case class Connect(loc: Node, exp: Arg) extends Command
+case class BulkConnect(loc1: Node, loc2: Node) extends Command
+case class Attach(locs: Seq[Node]) extends Command
+case class ConnectInit(loc: Node, exp: Arg) extends Command
 
 case class Port(id: Data, dir: SpecifiedDirection)
-case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
+case class Printf(id: printf.Printf, clock: Arg, pable: Printable) extends Definition
 object Formal extends Enumeration {
   val Assert = Value("assert")
   val Assume = Value("assume")