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authorAlbert Magyar2021-02-01 14:06:39 -0800
committerGitHub2021-02-01 22:06:39 +0000
commit98ce9194e5d87fdd5be931b6cd516d180a6540cd (patch)
treebabdfd24728a20188a170839d05d03b30aa11685 /core/src/main/scala/chisel3/internal
parent445b5cecb267adcd556627ffea2486b20740d6d4 (diff)
Update reported width from div/rem to match FIRRTL results (#1748)
* Update reported width from div/rem to match FIRRTL results * Add tests for width of % and / on UInt and SInt * Add loop-based test for known UInt/SInt op result widths Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'core/src/main/scala/chisel3/internal')
-rw-r--r--core/src/main/scala/chisel3/internal/firrtl/IR.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 095c8a05..61f97ce6 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -158,6 +158,7 @@ object Width {
sealed abstract class Width {
type W = Int
+ def min(that: Width): Width = this.op(that, _ min _)
def max(that: Width): Width = this.op(that, _ max _)
def + (that: Width): Width = this.op(that, _ + _)
def + (that: Int): Width = this.op(this, (a, b) => a + that)