diff options
| author | Deborah Soung | 2021-07-06 14:40:59 -0700 |
|---|---|---|
| committer | GitHub | 2021-07-06 14:40:59 -0700 |
| commit | 503ae520e7f997bcbc639b79869c9a4214d402ed (patch) | |
| tree | 7e72d44b7e023fac04fdbe8d95d5bfdc01001988 /core/src/main/scala/chisel3/internal | |
| parent | 4b7499f7c6287c696111bd7c6ee060f33f667419 (diff) | |
Make printf return BaseSim subclass so it can be named/annotated (#1992)
Diffstat (limited to 'core/src/main/scala/chisel3/internal')
| -rw-r--r-- | core/src/main/scala/chisel3/internal/firrtl/Converter.scala | 4 | ||||
| -rw-r--r-- | core/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index 093d4848..8efb2abc 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -143,10 +143,10 @@ private[chisel3] object Converter { Some(fir.DefInstance(convert(info), e.name, id.name)) case Stop(info, clock, ret) => Some(fir.Stop(convert(info), ret, convert(clock, ctx, info), firrtl.Utils.one)) - case Printf(info, clock, pable) => + case e @ Printf(_, info, clock, pable) => val (fmt, args) = unpack(pable, ctx) Some(fir.Print(convert(info), fir.StringLit(fmt), - args.map(a => convert(a, ctx, info)), convert(clock, ctx, info), firrtl.Utils.one)) + args.map(a => convert(a, ctx, info)), convert(clock, ctx, info), firrtl.Utils.one, e.name)) case e @ Verification(_, op, info, clk, pred, msg) => val firOp = op match { case Formal.Assert => fir.Formal.Assert diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index a4f6d26d..5796522c 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -773,7 +773,7 @@ case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command case class Port(id: Data, dir: SpecifiedDirection) -case class Printf(sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Command +case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition object Formal extends Enumeration { val Assert = Value("assert") val Assume = Value("assume") |