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authorJack2022-11-11 06:53:04 +0000
committerJack2022-11-11 06:53:04 +0000
commit3ce953c81f06519351c48277e3474b5720ec07ff (patch)
treeac79dcb80d0528c2ae86ca21da4cf424715ab645 /core/src/main/scala/chisel3/internal/MonoConnect.scala
parentadccde9998c91875e5490cff6d5822ffacc593ed (diff)
parentc8046636a25474be4c547c6fe9c6d742ea7b1d13 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'core/src/main/scala/chisel3/internal/MonoConnect.scala')
-rw-r--r--core/src/main/scala/chisel3/internal/MonoConnect.scala30
1 files changed, 22 insertions, 8 deletions
diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala
index 31364804..4e762a7c 100644
--- a/core/src/main/scala/chisel3/internal/MonoConnect.scala
+++ b/core/src/main/scala/chisel3/internal/MonoConnect.scala
@@ -322,21 +322,35 @@ private[chisel3] object MonoConnect {
else false
}
- /** Trace flow from child Data to its parent. */
- @tailrec private[chisel3] def traceFlow(currentlyFlipped: Boolean, data: Data, context_mod: RawModule): Boolean = {
- import SpecifiedDirection.{Input => SInput, Flip => SFlip}
+ /** Trace flow from child Data to its parent.
+ *
+ * Returns true if, given the context,
+ * this signal can be a sink when wantsToBeSink = true,
+ * or if it can be a source when wantsToBeSink = false.
+ * Always returns true if the Data does not actually correspond
+ * to a Port.
+ */
+ @tailrec private[chisel3] def traceFlow(
+ wantToBeSink: Boolean,
+ currentlyFlipped: Boolean,
+ data: Data,
+ context_mod: RawModule
+ ): Boolean = {
val sdir = data.specifiedDirection
- val flipped = sdir == SInput || sdir == SFlip
+ val coercedFlip = sdir == SpecifiedDirection.Input
+ val coercedAlign = sdir == SpecifiedDirection.Output
+ val flipped = sdir == SpecifiedDirection.Flip
+ val traceFlipped = ((flipped ^ currentlyFlipped) || coercedFlip) && (!coercedAlign)
data.binding.get match {
- case ChildBinding(parent) => traceFlow(flipped ^ currentlyFlipped, parent, context_mod)
+ case ChildBinding(parent) => traceFlow(wantToBeSink, traceFlipped, parent, context_mod)
case PortBinding(enclosure) =>
val childPort = enclosure != context_mod
- childPort ^ flipped ^ currentlyFlipped
+ wantToBeSink ^ childPort ^ traceFlipped
case _ => true
}
}
- def canBeSink(data: Data, context_mod: RawModule): Boolean = traceFlow(true, data, context_mod)
- def canBeSource(data: Data, context_mod: RawModule): Boolean = traceFlow(false, data, context_mod)
+ def canBeSink(data: Data, context_mod: RawModule): Boolean = traceFlow(true, false, data, context_mod)
+ def canBeSource(data: Data, context_mod: RawModule): Boolean = traceFlow(false, false, data, context_mod)
/** Check whether two aggregates can be bulk connected (<=) in FIRRTL. (MonoConnect case)
*