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authorJack2022-11-11 06:53:04 +0000
committerJack2022-11-11 06:53:04 +0000
commit3ce953c81f06519351c48277e3474b5720ec07ff (patch)
treeac79dcb80d0528c2ae86ca21da4cf424715ab645 /core/src/main/scala/chisel3/internal/BiConnect.scala
parentadccde9998c91875e5490cff6d5822ffacc593ed (diff)
parentc8046636a25474be4c547c6fe9c6d742ea7b1d13 (diff)
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'core/src/main/scala/chisel3/internal/BiConnect.scala')
-rw-r--r--core/src/main/scala/chisel3/internal/BiConnect.scala9
1 files changed, 6 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala
index e8fb2361..74376598 100644
--- a/core/src/main/scala/chisel3/internal/BiConnect.scala
+++ b/core/src/main/scala/chisel3/internal/BiConnect.scala
@@ -227,9 +227,12 @@ private[chisel3] object BiConnect {
context_mod: RawModule
): Unit = {
// Verify right has no extra fields that left doesn't have
- for ((field, right_sub) <- right_r.elements) {
- if (!left_r.elements.isDefinedAt(field)) {
- if (connectCompileOptions.connectFieldsMustMatch) {
+
+ // For each field in left, descend with right.
+ // Don't bother doing this check if we don't expect it to necessarily pass.
+ if (connectCompileOptions.connectFieldsMustMatch) {
+ for ((field, right_sub) <- right_r.elements) {
+ if (!left_r.elements.isDefinedAt(field)) {
throw MissingLeftFieldException(field)
}
}