Rename subprojects to more canonical names

* Rename coreMacros to macros
* Rename chiselFrontend to core

Also make each subproject publish with "chisel3-" as a prefix

2 files changed, 225 insertions, 0 deletions

diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala
new file mode 100644
index 00000000..37eb578d
--- /dev/null
+++ b/core/src/main/scala/chisel3/experimental/Analog.scala
@@ -0,0 +1,85 @@
+// See LICENSE for license details.
+
+package chisel3.experimental
+
+import chisel3.internal.firrtl.Width
+import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.internal._
+import chisel3.{ActualDirection, Bits, CompileOptions, Data, Element, PString, Printable, RawModule, SpecifiedDirection, UInt}
+
+import scala.collection.mutable
+
+/** Data type for representing bidirectional bitvectors of a given width
+  *
+  * Analog support is limited to allowing wiring up of Verilog BlackBoxes with bidirectional (inout)
+  * pins. There is currently no support for reading or writing of Analog types within Chisel code.
+  *
+  * Given that Analog is bidirectional, it is illegal to assign a direction to any Analog type. It
+  * is legal to "flip" the direction (since Analog can be a member of aggregate types) which has no
+  * effect.
+  *
+  * Analog types are generally connected using the bidirectional [[attach]] mechanism, but also
+  * support limited bulkconnect `<>`. Analog types are only allowed to be bulk connected *once* in a
+  * given module. This is to prevent any surprising consequences of last connect semantics.
+  *
+  * @note This API is experimental and subject to change
+  */
+final class Analog private (private[chisel3] val width: Width) extends Element {
+  require(width.known, "Since Analog is only for use in BlackBoxes, width must be known")
+
+  override def toString: String = {
+    s"Analog$width$bindingToString"
+  }
+
+  private[chisel3] override def typeEquivalent(that: Data): Boolean =
+    that.isInstanceOf[Analog] && this.width == that.width
+
+  override def litOption: Option[BigInt] = None
+
+  def cloneType: this.type = new Analog(width).asInstanceOf[this.type]
+
+  // Used to enforce single bulk connect of Analog types, multi-attach is still okay
+  // Note that this really means 1 bulk connect per Module because a port can
+  //   be connected in the parent module as well
+  private[chisel3] val biConnectLocs = mutable.Map.empty[RawModule, SourceInfo]
+
+  // Define setter/getter pairing
+  // Analog can only be bound to Ports and Wires (and Unbound)
+  private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) {
+    SpecifiedDirection.fromParent(parentDirection, specifiedDirection) match {
+      case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip =>
+      case x => throwException(s"Analog may not have explicit direction, got '$x'")
+    }
+    val targetTopBinding = target match {
+      case target: TopBinding => target
+      case ChildBinding(parent) => parent.topBinding
+      // See https://github.com/freechipsproject/chisel3/pull/946
+      case SampleElementBinding(parent) => parent.topBinding
+    }
+
+    targetTopBinding match {
+      case _: WireBinding | _: PortBinding => direction = ActualDirection.Bidirectional(ActualDirection.Default)
+      case x => throwException(s"Analog can only be Ports and Wires, not '$x'")
+    }
+    binding = target
+  }
+
+  override def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
+    throwException("Analog does not support asUInt")
+
+  private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
+      compileOptions: CompileOptions): Unit = {
+    throwException("Analog does not support connectFromBits")
+  }
+
+  def toPrintable: Printable = PString("Analog")
+}
+
+/** Object that provides factory methods for [[Analog]] objects
+  *
+  * @note This API is experimental and subject to change
+  */
+object Analog {
+  def apply(width: Width): Analog = new Analog(width)
+}
+
diff --git a/core/src/main/scala/chisel3/experimental/package.scala b/core/src/main/scala/chisel3/experimental/package.scala
new file mode 100644
index 00000000..985f7715
--- /dev/null
+++ b/core/src/main/scala/chisel3/experimental/package.scala
@@ -0,0 +1,140 @@
+// See LICENSE for license details.
+
+package chisel3
+
+/** Package for experimental features, which may have their API changed, be removed, etc.
+  *
+  * Because its contents won't necessarily have the same level of stability and support as
+  * non-experimental, you must explicitly import this package to use its contents.
+  */
+package object experimental {  // scalastyle:ignore object.name
+  import scala.language.implicitConversions
+  import chisel3.internal.BaseModule
+
+  // Implicit conversions for BlackBox Parameters
+  implicit def fromIntToIntParam(x: Int): IntParam = IntParam(BigInt(x))
+  implicit def fromLongToIntParam(x: Long): IntParam = IntParam(BigInt(x))
+  implicit def fromBigIntToIntParam(x: BigInt): IntParam = IntParam(x)
+  implicit def fromDoubleToDoubleParam(x: Double): DoubleParam = DoubleParam(x)
+  implicit def fromStringToStringParam(x: String): StringParam = StringParam(x)
+
+  type ChiselEnum = EnumFactory
+
+  @deprecated("Use the version in chisel3._", "3.2")
+  val withClockAndReset = chisel3.withClockAndReset
+  @deprecated("Use the version in chisel3._", "3.2")
+  val withClock = chisel3.withClock
+  @deprecated("Use the version in chisel3._", "3.2")
+  val withReset = chisel3.withReset
+
+  // Rocket Chip-style clonemodule
+
+  /** A record containing the results of CloneModuleAsRecord
+    * The apply method is retrieves the element with the supplied name.
+    */
+  type ClonePorts = BaseModule.ClonePorts
+
+  object CloneModuleAsRecord {
+    /** Clones an existing module and returns a record of all its top-level ports.
+      * Each element of the record is named with a string matching the
+      * corresponding port's name and shares the port's type.
+      * @example {{{
+      * val q1 = Module(new Queue(UInt(32.W), 2))
+      * val q2_io = CloneModuleAsRecord(q1)("io").asInstanceOf[q1.io.type]
+      * q2_io.enq <> q1.io.deq
+      * }}}
+      */
+    def apply(proto: BaseModule)(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): ClonePorts = { // scalastyle:ignore line.size.limit
+      BaseModule.cloneIORecord(proto)
+    }
+  }
+
+  val requireIsHardware = chisel3.internal.requireIsHardware
+  val requireIsChiselType =  chisel3.internal.requireIsChiselType
+  type Direction = ActualDirection
+  val Direction = ActualDirection
+
+  implicit class ChiselRange(val sc: StringContext) extends AnyVal {
+
+    import scala.language.experimental.macros
+
+    /** Specifies a range using mathematical range notation. Variables can be interpolated using
+      * standard string interpolation syntax.
+      * @example {{{
+      * UInt(range"[0, 2)")
+      * UInt(range"[0, \$myInt)")
+      * UInt(range"[0, \${myInt + 2})")
+      * }}}
+      */
+    def range(args: Any*): chisel3.internal.firrtl.IntervalRange = macro chisel3.internal.RangeTransform.apply
+  }
+
+  class dump extends chisel3.internal.naming.dump  // scalastyle:ignore class.name
+  class treedump extends chisel3.internal.naming.treedump  // scalastyle:ignore class.name
+  /** Experimental macro for naming Chisel hardware values
+    *
+    * By default, Chisel uses reflection for naming which only works for public fields of `Bundle`
+    * and `Module` classes. Applying this macro annotation to a `class` or `object` enables Chisel
+    * to name any hardware values within the annotated `class` or `object.
+    *
+    * @example {{{
+    * import chisel3._
+    * import chisel3.experimental.chiselName
+    *
+    * @chiselName
+    * class MyModule extends Module {
+    *   val io = IO(new Bundle {
+    *     val in = Input(UInt(8.W))
+    *     val out = Output(UInt(8.W))
+    *   })
+    *   def createReg(): Unit = {
+    *     // @chiselName allows Chisel to name this Reg
+    *     val myReg = RegInit(io.in)
+    *     io.out := myReg
+    *   }
+    *   createReg()
+    * }
+    * }}}
+    */
+  class chiselName extends chisel3.internal.naming.chiselName  // scalastyle:ignore class.name
+  /** Do not name instances of this type in [[chiselName]]
+    *
+    * By default, `chiselName` will include `val` names of instances of annotated classes as a
+    * prefix in final naming. Mixing in this trait to a `class`, `object`, or anonymous `class`
+    * instances will exclude the `val` name from `chiselName` naming.
+    *
+    * @example {{{
+    * import chisel3._
+    * import chisel3.experimental.{chiselName, NoChiselNamePrefix}
+    *
+    * // Note that this is not a Module
+    * @chiselName
+    * class Counter(w: Int) {
+    *   val myReg = RegInit(0.U(w.W))
+    *   myReg := myReg + 1.U
+    * }
+    *
+    * @chiselName
+    * class MyModule extends Module {
+    *   val io = IO(new Bundle {
+    *     val out = Output(UInt(8.W))
+    *   })
+    *   // Name of myReg will be "counter0_myReg"
+    *   val counter0 = new Counter(8)
+    *   // Name of myReg will be "myReg"
+    *   val counter1 = new Counter(8) with NoChiselNamePrefix
+    *   io.out := counter0.myReg + counter1.myReg
+    * }
+    * }}}
+    */
+  trait NoChiselNamePrefix
+
+  object BundleLiterals {
+    implicit class AddBundleLiteralConstructor[T <: Bundle](x: T) {
+      //scalastyle:off method.name
+      def Lit(elems: (T => (Data, Data))*): T = {
+        x._makeLit(elems: _*)
+      }
+    }
+  }
+}