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| author | Jack Koenig | 2021-02-10 13:49:25 -0800 |
|---|---|---|
| committer | GitHub | 2021-02-10 13:49:25 -0800 |
| commit | f41e762830c5af1a92de9d8ee26e2b0de52b76ad (patch) | |
| tree | 89a42cf3ae9eb96b02a54bc83040c04cd1ea294d /core/src/main/scala/chisel3/experimental | |
| parent | 2ed343e2305b7c22000f3f46fa81d73a369907eb (diff) | |
| parent | 0a0d7c6aac4326f2127d6d95efa5a4e10c81946c (diff) | |
Merge pull request #1624 from chipsalliance/gc-data
Make Data GC-able
Diffstat (limited to 'core/src/main/scala/chisel3/experimental')
| -rw-r--r-- | core/src/main/scala/chisel3/experimental/Analog.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala index df76fd70..2ce2c86d 100644 --- a/core/src/main/scala/chisel3/experimental/Analog.scala +++ b/core/src/main/scala/chisel3/experimental/Analog.scala @@ -45,7 +45,8 @@ final class Analog private (private[chisel3] val width: Width) extends Element { // Define setter/getter pairing // Analog can only be bound to Ports and Wires (and Unbound) - private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { + private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection): Unit = { + _parent.foreach(_.addId(this)) SpecifiedDirection.fromParent(parentDirection, specifiedDirection) match { case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => case x => throwException(s"Analog may not have explicit direction, got '$x'") |