Emit FIRRTL bulkconnects whenever possible (#2381) (#2440)

Chisel <> semantics differ somewhat from FIRRTL <= semantics,
so we only emit <= when it would be legal. Otherwise we continue
the old behavior of emitting a connection for every leaf-level
Element.

Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 3553a1583403824718923a6cc530cec3b38f5704)

Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/core/src/main/scala/chisel3/experimental/dataview/package.scala b/core/src/main/scala/chisel3/experimental/dataview/package.scala
index 3278d82c..891ecb81 100644
--- a/core/src/main/scala/chisel3/experimental/dataview/package.scala
+++ b/core/src/main/scala/chisel3/experimental/dataview/package.scala
@@ -262,4 +262,14 @@ package object dataview {
     }
   }
 
+  /** Determine the target of a View if it is a single Target
+    *
+    * @note An Aggregate may be a view of unrelated [[Data]] (eg. like a Seq or tuple) and thus this
+    *       there is no single Data representing the Target and this function will return None
+    * @return The single Data target of this view or None if a single Data doesn't exist
+    */
+  private[chisel3] def reifyToAggregate(data: Data): Option[Aggregate] = reifySingleData(data) match {
+    case Some(a: Aggregate) => Some(a)
+    case other => None
+  }
 }