diff options
| author | mergify[bot] | 2022-11-05 22:31:07 +0000 |
|---|---|---|
| committer | GitHub | 2022-11-05 22:31:07 +0000 |
| commit | 017bd6b9c96974df2a3c4f35e069d60fec001f2e (patch) | |
| tree | 8dab4e44284af8a0904f0817c1875a9b73243328 /core/src/main/scala/chisel3/experimental | |
| parent | 4149157df6531d124483d992daf96cf4e62a0f0c (diff) | |
Support Analog in DataView (#2782) (#2828)
Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 26100a875c69bf56f7442fac82ca9c74ad3596eb)
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'core/src/main/scala/chisel3/experimental')
| -rw-r--r-- | core/src/main/scala/chisel3/experimental/Analog.scala | 3 | ||||
| -rw-r--r-- | core/src/main/scala/chisel3/experimental/Attach.scala | 45 |
2 files changed, 47 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala index a366f0c3..7d89025c 100644 --- a/core/src/main/scala/chisel3/experimental/Analog.scala +++ b/core/src/main/scala/chisel3/experimental/Analog.scala @@ -69,7 +69,8 @@ final class Analog private (private[chisel3] val width: Width) extends Element { } targetTopBinding match { - case _: WireBinding | _: PortBinding => direction = ActualDirection.Bidirectional(ActualDirection.Default) + case _: WireBinding | _: PortBinding | _: ViewBinding | _: AggregateViewBinding => + direction = ActualDirection.Bidirectional(ActualDirection.Default) case x => throwException(s"Analog can only be Ports and Wires, not '$x'") } binding = target diff --git a/core/src/main/scala/chisel3/experimental/Attach.scala b/core/src/main/scala/chisel3/experimental/Attach.scala new file mode 100644 index 00000000..5c9cfe53 --- /dev/null +++ b/core/src/main/scala/chisel3/experimental/Attach.scala @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chisel3.experimental + +import chisel3.RawModule +import chisel3.internal._ +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.SourceInfo + +object attach { + // Exceptions that can be generated by attach + case class AttachException(message: String) extends ChiselException(message) + def ConditionalAttachException: AttachException = + AttachException(": Conditional attach is not allowed!") + + // Actual implementation + private[chisel3] def impl(elts: Seq[Analog], contextModule: RawModule)(implicit sourceInfo: SourceInfo): Unit = { + if (Builder.whenDepth != 0) throw ConditionalAttachException + + // TODO Check that references are valid and can be attached + + pushCommand(Attach(sourceInfo, elts.map(_.lref))) + } + + /** Create an electrical connection between [[Analog]] components + * + * @param elts The components to attach + * + * @example + * {{{ + * val a1 = Wire(Analog(32.W)) + * val a2 = Wire(Analog(32.W)) + * attach(a1, a2) + * }}} + */ + def apply(elts: Analog*)(implicit sourceInfo: SourceInfo): Unit = { + try { + impl(elts, Builder.forcedUserModule) + } catch { + case AttachException(message) => + throwException(elts.mkString("Attaching (", ", ", s") failed @$message")) + } + } +} |
