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authorJack Koenig2022-01-10 10:39:52 -0800
committerJack Koenig2022-01-10 15:53:55 -0800
commit3131c0daad41dea78bede4517669e376c41a325a (patch)
tree55baed78a6a01f80ff3952a08233ca553a19964f /core/src/main/scala/chisel3/experimental/Analog.scala
parentdd36f97a82746cec0b25b94651581fe799e24579 (diff)
Apply scalafmt
Command: sbt scalafmtAll
Diffstat (limited to 'core/src/main/scala/chisel3/experimental/Analog.scala')
-rw-r--r--core/src/main/scala/chisel3/experimental/Analog.scala23
1 files changed, 19 insertions, 4 deletions
diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala
index e94bae2d..a366f0c3 100644
--- a/core/src/main/scala/chisel3/experimental/Analog.scala
+++ b/core/src/main/scala/chisel3/experimental/Analog.scala
@@ -5,7 +5,18 @@ package chisel3.experimental
import chisel3.internal.firrtl.Width
import chisel3.internal.sourceinfo.SourceInfo
import chisel3.internal._
-import chisel3.{ActualDirection, Bits, CompileOptions, Data, Element, PString, Printable, RawModule, SpecifiedDirection, UInt}
+import chisel3.{
+ ActualDirection,
+ Bits,
+ CompileOptions,
+ Data,
+ Element,
+ PString,
+ Printable,
+ RawModule,
+ SpecifiedDirection,
+ UInt
+}
import scala.collection.mutable
@@ -47,7 +58,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
_parent.foreach(_.addId(this))
SpecifiedDirection.fromParent(parentDirection, specifiedDirection) match {
case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip =>
- case x => throwException(s"Analog may not have explicit direction, got '$x'")
+ case x => throwException(s"Analog may not have explicit direction, got '$x'")
}
val targetTopBinding = target match {
case target: TopBinding => target
@@ -67,8 +78,12 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
override def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
throwException("Analog does not support asUInt")
- private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
- compileOptions: CompileOptions): Unit = {
+ private[chisel3] override def connectFromBits(
+ that: Bits
+ )(
+ implicit sourceInfo: SourceInfo,
+ compileOptions: CompileOptions
+ ): Unit = {
throwException("Analog does not support connectFromBits")
}