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authorJack Koenig2022-01-10 10:39:52 -0800
committerJack Koenig2022-01-10 15:53:55 -0800
commit3131c0daad41dea78bede4517669e376c41a325a (patch)
tree55baed78a6a01f80ff3952a08233ca553a19964f /core/src/main/scala/chisel3/UIntFactory.scala
parentdd36f97a82746cec0b25b94651581fe799e24579 (diff)
Apply scalafmt
Command: sbt scalafmtAll
Diffstat (limited to 'core/src/main/scala/chisel3/UIntFactory.scala')
-rw-r--r--core/src/main/scala/chisel3/UIntFactory.scala7
1 files changed, 5 insertions, 2 deletions
diff --git a/core/src/main/scala/chisel3/UIntFactory.scala b/core/src/main/scala/chisel3/UIntFactory.scala
index e0f3dc92..64127991 100644
--- a/core/src/main/scala/chisel3/UIntFactory.scala
+++ b/core/src/main/scala/chisel3/UIntFactory.scala
@@ -9,8 +9,10 @@ import firrtl.ir.{Closed, IntWidth, Open}
// This is currently a factory because both Bits and UInt inherit it.
trait UIntFactory {
+
/** Create a UInt type with inferred width. */
def apply(): UInt = apply(Width())
+
/** Create a UInt port with specified width. */
def apply(width: Width): UInt = new UInt(width)
@@ -21,6 +23,7 @@ trait UIntFactory {
// Bind result to being an Literal
lit.bindLitArg(result)
}
+
/** Create a UInt with the specified range, validate that range is effectively > 0
*/
def apply(range: IntervalRange): UInt = {
@@ -34,8 +37,8 @@ trait UIntFactory {
}
// because this is a UInt we don't have to take into account the lower bound
- val newWidth = if(range.upperBound.isInstanceOf[IsKnown]) {
- KnownWidth(Utils.getUIntWidth(range.maxAdjusted.get).max(1)) // max(1) handles range"[0,0]"
+ val newWidth = if (range.upperBound.isInstanceOf[IsKnown]) {
+ KnownWidth(Utils.getUIntWidth(range.maxAdjusted.get).max(1)) // max(1) handles range"[0,0]"
} else {
UnknownWidth()
}