Get cleanup to compile

1 files changed, 1 insertions, 6 deletions

diff --git a/core/src/main/scala/chisel3/SIntFactory.scala b/core/src/main/scala/chisel3/SIntFactory.scala
index 3fafacda..8cceda13 100644
--- a/core/src/main/scala/chisel3/SIntFactory.scala
+++ b/core/src/main/scala/chisel3/SIntFactory.scala
@@ -2,7 +2,7 @@
 
 package chisel3
 
-import chisel3.internal.firrtl.{IntervalRange, SLit, Width}
+import chisel3.internal.firrtl.{SLit, Width}
 
 trait SIntFactory {
 
@@ -12,11 +12,6 @@ trait SIntFactory {
   /** Create a SInt type or port with fixed width. */
   def apply(width: Width): SInt = new SInt(width)
 
-  /** Create a SInt with the specified range */
-  def apply(range: IntervalRange): SInt = {
-    apply(range.getWidth)
-  }
-
   /** Create an SInt literal with specified width. */
   protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
     val lit = SLit(value, width)