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| author | Jack | 2022-01-12 04:27:19 +0000 |
|---|---|---|
| committer | Jack | 2022-01-12 04:27:19 +0000 |
| commit | 29df513e348cc809876893f650af8180f0190496 (patch) | |
| tree | 06daaea954b4e5af7113f06e4bdbb78b33515cb3 /core/src/main/scala/chisel3/SIntFactory.scala | |
| parent | 5242ce90659decb9058ee75db56e5c188029fbf9 (diff) | |
| parent | 747d16311bdf185d2e98e452b14cb5d8ccca004c (diff) | |
Merge branch 'master' into 3.5-release
Diffstat (limited to 'core/src/main/scala/chisel3/SIntFactory.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/SIntFactory.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/SIntFactory.scala b/core/src/main/scala/chisel3/SIntFactory.scala index b34c7dde..3fafacda 100644 --- a/core/src/main/scala/chisel3/SIntFactory.scala +++ b/core/src/main/scala/chisel3/SIntFactory.scala @@ -5,8 +5,10 @@ package chisel3 import chisel3.internal.firrtl.{IntervalRange, SLit, Width} trait SIntFactory { + /** Create an SInt type with inferred width. */ def apply(): SInt = apply(Width()) + /** Create a SInt type or port with fixed width. */ def apply(width: Width): SInt = new SInt(width) |