diff options
| author | Albert Magyar | 2020-07-31 11:05:13 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-31 18:05:13 +0000 |
| commit | 5ecde24d390248722f8ab6ac790fbd1d453e898e (patch) | |
| tree | e92d337431500ea06392acd0731f7c021662f6e6 /core/src/main/scala/chisel3/Reg.scala | |
| parent | 8990ca3d8d8434a6c979b0c5fc06b05a39fd31d4 (diff) | |
Check whether signals escape their when scopes (#1518)
* Include and check when scoping as part of reg/mem/wire/node bindings
* Allow outdated 'when' behavior of CHIRRTL memory ports with enables
* Extend cross-module / when-visibility checks to all data refs
* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args
* Add basic test cases for cross-module refs / signals escaping when scopes
* Remove illegal cross-module references from existing tests
Diffstat (limited to 'core/src/main/scala/chisel3/Reg.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/Reg.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala index 7129c389..f57281d6 100644 --- a/core/src/main/scala/chisel3/Reg.scala +++ b/core/src/main/scala/chisel3/Reg.scala @@ -41,7 +41,7 @@ object Reg { val reg = t.cloneTypeFull val clock = Node(Builder.forcedClock) - reg.bind(RegBinding(Builder.forcedUserModule)) + reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen())) pushCommand(DefReg(sourceInfo, reg, clock)) reg } @@ -174,7 +174,7 @@ object RegInit { val clock = Builder.forcedClock val reset = Builder.forcedReset - reg.bind(RegBinding(Builder.forcedUserModule)) + reg.bind(RegBinding(Builder.forcedUserModule, Builder.currentWhen())) requireIsHardware(init, "reg initializer") pushCommand(DefRegInit(sourceInfo, reg, clock.ref, reset.ref, init.ref)) reg |