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| author | Jack Koenig | 2021-02-10 13:49:25 -0800 |
|---|---|---|
| committer | GitHub | 2021-02-10 13:49:25 -0800 |
| commit | f41e762830c5af1a92de9d8ee26e2b0de52b76ad (patch) | |
| tree | 89a42cf3ae9eb96b02a54bc83040c04cd1ea294d /core/src/main/scala/chisel3/RawModule.scala | |
| parent | 2ed343e2305b7c22000f3f46fa81d73a369907eb (diff) | |
| parent | 0a0d7c6aac4326f2127d6d95efa5a4e10c81946c (diff) | |
Merge pull request #1624 from chipsalliance/gc-data
Make Data GC-able
Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/RawModule.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index 0adacedb..d2ba6e84 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -98,6 +98,8 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) id._onModuleClose } + closeUnboundIds(names) + val firrtlPorts = getModulePorts map { port: Data => // Special case Vec to make FIRRTL emit the direction of its // element. |