diff options
| author | Aditya Naik | 2021-10-20 00:13:34 -0400 |
|---|---|---|
| committer | GitHub | 2021-10-20 04:13:34 +0000 |
| commit | d6907893f019ee86573dc81768884150e541dba3 (patch) | |
| tree | 68d8a79fcc18e62a8ffb0605546f179ba8e3c1b2 /core/src/main/scala/chisel3/RawModule.scala | |
| parent | 5c4c43502eb0723d71b8ee1df9faab0e477e17a0 (diff) | |
Update computeName and callsites (#2192)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/RawModule.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index c001772b..d8781ee0 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -44,7 +44,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) private[chisel3] def namePorts(names: HashMap[HasId, String]): Unit = { for (port <- getModulePorts) { - port.computeName(None, None).orElse(names.get(port)) match { + port._computeName(None, None).orElse(names.get(port)) match { case Some(name) => if (_namespace.contains(name)) { Builder.error(s"""Unable to name port $port to "$name" in $this,""" + |