diff options
| author | Aditya Naik | 2024-05-29 17:28:22 -0700 |
|---|---|---|
| committer | Aditya Naik | 2024-05-29 17:28:22 -0700 |
| commit | bc92bb62f9f6a090e74392993e4fcfdd1f6b0676 (patch) | |
| tree | 160eb4cc2770eaf0c189fab9442d04b2b00b7919 /core/src/main/scala/chisel3/RawModule.scala | |
| parent | 878d488a7c8e0d6973de58b3164022c6a102e449 (diff) | |
i got 99 errors but "firrtl not found" aint one
Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/RawModule.scala | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index 19b719e0..71bbcd00 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -3,7 +3,6 @@ package chisel3 import scala.util.Try -import scala.language.experimental.macros import scala.annotation.nowarn import chisel3.experimental.BaseModule import chisel3.internal._ @@ -25,7 +24,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends // Perhaps this should be an ArrayBuffer (or ArrayBuilder), but DefModule is public and has Seq[Command] // so our best option is to share a single Seq datastructure with that private val _commands = new VectorBuilder[Command]() - private[chisel3] def addCommand(c: Command) { + private[chisel3] def addCommand(c: Command) = { require(!_closed, "Can't write to module after module close") _commands += c } @@ -48,7 +47,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends case b: BaseModule => true case m: MemBase[_] => true // These names don't affect hardware - case _: VerificationStatement => false + // case _: VerificationStatement => false // While the above should be comprehensive, since this is used in warning we want to be careful // to never accidentally have a match error case _ => false @@ -86,10 +85,10 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends id match { case id: BaseModule => id.forceName(default = id.desiredName, _namespace) case id: MemBase[_] => id.forceName(default = "MEM", _namespace) - case id: stop.Stop => id.forceName(default = "stop", _namespace) - case id: assert.Assert => id.forceName(default = "assert", _namespace) - case id: assume.Assume => id.forceName(default = "assume", _namespace) - case id: cover.Cover => id.forceName(default = "cover", _namespace) + // removed till macros are fixed + // case id: assert.Assert => id.forceName(default = "assert", _namespace) + // case id: assume.Assume => id.forceName(default = "assume", _namespace) + // case id: cover.Cover => id.forceName(default = "cover", _namespace) case id: printf.Printf => id.forceName(default = "printf", _namespace) case id: Data => if (id.isSynthesizable) { |