Remove sourceinfo, compileoptions and other fixes

35 erros

1 files changed, 2 insertions, 5 deletions

diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 71bbcd00..01e5f9f5 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -8,7 +8,6 @@ import chisel3.experimental.BaseModule
 import chisel3.internal._
 import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
-import chisel3.internal.sourceinfo.UnlocatableSourceInfo
 import _root_.firrtl.annotations.{IsModule, ModuleTarget}
 import scala.collection.immutable.VectorBuilder
 
@@ -17,7 +16,7 @@ import scala.collection.immutable.VectorBuilder
   * multiple IO() declarations.
   */
 @nowarn("msg=class Port") // delete when Port becomes private
-abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends BaseModule {
+abstract class RawModule extends BaseModule {
   //
   // RTL construction internals
   //
@@ -35,8 +34,6 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
     _component.get.asInstanceOf[DefModule].commands
   }
 
-  val compileOptions = moduleCompileOptions
-
   // This could be factored into a common utility
   private def canBeNamed(id: HasId): Boolean = id match {
     case d: Data =>
@@ -117,7 +114,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
     _component
   }
 
-  private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {}
+  private[chisel3] def initializeInParent: Unit = {}
 }
 
 trait RequireAsyncReset extends Module {