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authorJack Koenig2021-08-30 18:56:33 -0700
committerGitHub2021-08-31 01:56:33 +0000
commit7fb2c1ebc23ca07e5de6416a284e1be1b62a48ac (patch)
tree49a098a3d02cbc952be81d0266ec0351cab6922f /core/src/main/scala/chisel3/RawModule.scala
parent29665743acff120bc87ee997890d7f952317144e (diff)
Fix chisel3 <> for compatibility Bundles (Take 3) (#2093)
Previous incomplete fixes in #2023 and #2031. The legality of a FIRRTL connection is determined by type and flow. Chisel does not have access to true flow information. Previous fix attempts tried to use ActualDirection as a stand-in for flow, but it is incorrect in many cases. This new approach checks the flows of the lvalue and rvalues in the connect and flips the connection if either the lvalue cannot be a sink or the rvalue cannot be a source.
Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
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