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authorAlbert Magyar2020-07-20 12:11:44 -0700
committerAlbert Magyar2020-07-21 13:06:53 -0700
commit7e9f424fb7dcd11c894ceb9f6f049fd9eda80632 (patch)
tree1fa15e357d0af7b82316fa2ee659e2e98118488c /core/src/main/scala/chisel3/RawModule.scala
parent4a0e828cfe76e0d3bd6c4a0cc593589fe74ed0ba (diff)
Delete outdated scalastyle configuration comments from source
Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
-rw-r--r--core/src/main/scala/chisel3/RawModule.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 218022cc..0fcec266 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -58,7 +58,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
}
- private[chisel3] override def generateComponent(): Component = { // scalastyle:ignore cyclomatic.complexity
+ private[chisel3] override def generateComponent(): Component = {
require(!_closed, "Can't generate module more than once")
_closed = true
@@ -194,7 +194,7 @@ package internal {
def io: Record
// Allow access to bindings from the compatibility package
- protected def _compatIoPortBound() = portsContains(io)// scalastyle:ignore method.name
+ protected def _compatIoPortBound() = portsContains(io)
private[chisel3] override def namePorts(names: HashMap[HasId, String]): Unit = {
for (port <- getModulePorts) {
@@ -211,7 +211,7 @@ package internal {
// Restrict IO to just io, clock, and reset
require(io != null, "Module must have io")
require(portsContains(io), "Module must have io wrapped in IO(...)")
- require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") // scalastyle:ignore line.size.limit
+ require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO")
require(portsSize == 3, "Module must only have io, clock, and reset as IO")
super.generateComponent()