diff options
| author | Jack Koenig | 2021-12-15 13:02:12 -0800 |
|---|---|---|
| committer | GitHub | 2021-12-15 21:02:12 +0000 |
| commit | 4ff431bb5c7978c9915bcd6080a4f27ef12ae607 (patch) | |
| tree | 6fe4a2c21f886fe9a7ddcff46cdbc2bb05f26bca /core/src/main/scala/chisel3/RawModule.scala | |
| parent | 8a60679bd742f6824a73e93811e423aa7feccc43 (diff) | |
Restore Port to public API and deprecate (#2302)
Also clean up deprecation warnings for replacement APIs and add
clarifying ScalaDoc.
Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/RawModule.scala | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index d8781ee0..e977d918 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -5,6 +5,7 @@ package chisel3 import scala.collection.mutable.{ArrayBuffer, HashMap} import scala.util.Try import scala.language.experimental.macros +import scala.annotation.nowarn import chisel3.experimental.BaseModule import chisel3.internal._ import chisel3.internal.BaseModule.{ModuleClone, InstanceClone} @@ -17,6 +18,7 @@ import _root_.firrtl.annotations.{IsModule, ModuleTarget} * This abstract base class is a user-defined module which does not include implicit clock and reset and supports * multiple IO() declarations. */ +@nowarn("msg=class Port") // delete when Port becomes private abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends BaseModule { // @@ -35,10 +37,10 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) // // Other Internal Functions // - // For debuggers/testers, TODO: refactor out into proper public API private var _firrtlPorts: Option[Seq[firrtl.Port]] = None - @deprecated("Use DataMirror.fullModulePorts instead. this API will be removed in Chisel 3.6", "Chisel 3.5") - lazy val getPorts = _firrtlPorts.get + + @deprecated("Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6", "Chisel 3.5") + lazy val getPorts: Seq[Port] = _firrtlPorts.get val compileOptions = moduleCompileOptions |