diff options
| author | Adam Izraelevitz | 2020-07-29 20:48:31 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-29 20:48:31 -0700 |
| commit | 164490c8fbf132ca65644d05d6ff8d0d7a3beb20 (patch) | |
| tree | 862750b85dca5b8496c40c24b3a4e5e67c268bd4 /core/src/main/scala/chisel3/RawModule.scala | |
| parent | 8aeb39b9b3755ccd0e3aa600b813ed4220ac72d8 (diff) | |
Improved Chisel Naming via Compiler Plugins + Prefixing (#1448)
Added prefixing and a compiler plugin to improve naming. Only works for Scala 2.12 and above.
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/RawModule.scala | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index 0fcec266..5b609384 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -42,7 +42,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) private[chisel3] def namePorts(names: HashMap[HasId, String]): Unit = { for (port <- getModulePorts) { - port.suggestedName.orElse(names.get(port)) match { + port.computeName(None, None).orElse(names.get(port)) match { case Some(name) => if (_namespace.contains(name)) { Builder.error(s"""Unable to name port $port to "$name" in $this,""" + @@ -75,13 +75,21 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) // All suggestions are in, force names to every node. for (id <- getIds) { id match { - case id: BaseModule => id.forceName(default=id.desiredName, _namespace) - case id: MemBase[_] => id.forceName(default="_T", _namespace) + case id: BaseModule => id.forceName(None, default=id.desiredName, _namespace) + case id: MemBase[_] => id.forceName(None, default="MEM", _namespace) case id: Data => if (id.isSynthesizable) { id.topBinding match { - case OpBinding(_) | MemoryPortBinding(_) | PortBinding(_) | RegBinding(_) | WireBinding(_) => - id.forceName(default="_T", _namespace) + case OpBinding(_) => + id.forceName(Some(""), default="T", _namespace) + case MemoryPortBinding(_) => + id.forceName(None, default="MPORT", _namespace) + case PortBinding(_) => + id.forceName(None, default="PORT", _namespace) + case RegBinding(_) => + id.forceName(None, default="REG", _namespace) + case WireBinding(_) => + id.forceName(Some(""), default="WIRE", _namespace) case _ => // don't name literals } } // else, don't name unbound types @@ -152,8 +160,8 @@ trait RequireSyncReset extends MultiIOModule { abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions) extends RawModule { // Implicit clock and reset pins - final val clock: Clock = IO(Input(Clock())) - final val reset: Reset = IO(Input(mkReset)) + final val clock: Clock = IO(Input(Clock())).autoSeed("clock") + final val reset: Reset = IO(Input(mkReset)).autoSeed("reset") private[chisel3] def mkReset: Reset = { // Top module and compatibility mode use Bool for reset @@ -164,6 +172,7 @@ abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions) // Setup ClockAndReset Builder.currentClock = Some(clock) Builder.currentReset = Some(reset) + Builder.clearPrefix() private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { implicit val sourceInfo = UnlocatableSourceInfo |