summaryrefslogtreecommitdiff
path: root/core/src/main/scala/chisel3/Printf.scala
diff options
context:
space:
mode:
authorDeborah Soung2021-07-06 14:40:59 -0700
committerGitHub2021-07-06 14:40:59 -0700
commit503ae520e7f997bcbc639b79869c9a4214d402ed (patch)
tree7e72d44b7e023fac04fdbe8d95d5bfdc01001988 /core/src/main/scala/chisel3/Printf.scala
parent4b7499f7c6287c696111bd7c6ee060f33f667419 (diff)
Make printf return BaseSim subclass so it can be named/annotated (#1992)
Diffstat (limited to 'core/src/main/scala/chisel3/Printf.scala')
-rw-r--r--core/src/main/scala/chisel3/Printf.scala22
1 files changed, 14 insertions, 8 deletions
diff --git a/core/src/main/scala/chisel3/Printf.scala b/core/src/main/scala/chisel3/Printf.scala
index 7cbd1918..cf7821b8 100644
--- a/core/src/main/scala/chisel3/Printf.scala
+++ b/core/src/main/scala/chisel3/Printf.scala
@@ -3,11 +3,10 @@
package chisel3
import scala.language.experimental.macros
-
import chisel3.internal._
import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl._
import chisel3.internal.sourceinfo.SourceInfo
+import chisel3.experimental.BaseSim
/** Prints a message in simulation
*
@@ -34,6 +33,9 @@ object printf {
formatIn map escaped mkString ""
}
+ /** Named class for [[printf]]s. */
+ final class Printf(val pable: Printable) extends BaseSim
+
/** Prints a message in simulation
*
* Prints a message every cycle. If defined within the scope of a [[when]] block, the message
@@ -71,7 +73,7 @@ object printf {
* @param fmt printf format string
* @param data format string varargs containing data to print
*/
- def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit =
+ def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Printf =
apply(Printable.pack(fmt, data:_*))
/** Prints a message in simulation
*
@@ -87,16 +89,20 @@ object printf {
* @see [[Printable]] documentation
* @param pable [[Printable]] to print
*/
- def apply(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = {
+ def apply(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Printf = {
+ var printfId: Printf = null
when (!Module.reset.asBool) {
- printfWithoutReset(pable)
+ printfId = printfWithoutReset(pable)
}
+ printfId
}
- private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = {
+ private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Printf = {
val clock = Builder.forcedClock
- pushCommand(Printf(sourceInfo, clock.ref, pable))
+ val printfId = new Printf(pable)
+ pushCommand(chisel3.internal.firrtl.Printf(printfId, sourceInfo, clock.ref, pable))
+ printfId
}
- private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit =
+ private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Printf =
printfWithoutReset(Printable.pack(fmt, data:_*))
}