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| author | Aditya Naik | 2024-05-29 17:28:22 -0700 |
|---|---|---|
| committer | Aditya Naik | 2024-05-29 17:28:22 -0700 |
| commit | bc92bb62f9f6a090e74392993e4fcfdd1f6b0676 (patch) | |
| tree | 160eb4cc2770eaf0c189fab9442d04b2b00b7919 /core/src/main/scala/chisel3/MultiClock.scala | |
| parent | 878d488a7c8e0d6973de58b3164022c6a102e449 (diff) | |
i got 99 errors but "firrtl not found" aint one
Diffstat (limited to 'core/src/main/scala/chisel3/MultiClock.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/MultiClock.scala | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/core/src/main/scala/chisel3/MultiClock.scala b/core/src/main/scala/chisel3/MultiClock.scala index e96946f5..4809cf29 100644 --- a/core/src/main/scala/chisel3/MultiClock.scala +++ b/core/src/main/scala/chisel3/MultiClock.scala @@ -4,8 +4,6 @@ package chisel3 import chisel3.internal._ -import scala.language.experimental.macros - object withClockAndReset { /** Creates a new Clock and Reset scope |