Merge pull request #2246 from chipsalliance/scalafmt

Add scalafmt configuration and apply it.

1 files changed, 106 insertions, 75 deletions

diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 7ba24585..3611f5dd 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -15,6 +15,7 @@ import _root_.firrtl.annotations.{IsModule, ModuleName, ModuleTarget}
 import _root_.firrtl.AnnotationSeq
 
 object Module extends SourceInfoDoc {
+
   /** A wrapper method that all Module instantiations must be wrapped in
     * (necessary to help Chisel track internal state).
     *
@@ -25,12 +26,12 @@ object Module extends SourceInfoDoc {
   def apply[T <: BaseModule](bc: => T): T = macro InstTransform.apply[T]
 
   /** @group SourceInfoTransformMacro */
-  def do_apply[T <: BaseModule](bc: => T)
-                               (implicit sourceInfo: SourceInfo,
-                                         compileOptions: CompileOptions): T = {
+  def do_apply[T <: BaseModule](bc: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
     if (Builder.readyForModuleConstr) {
-      throwException("Error: Called Module() twice without instantiating a Module." +
-                     sourceInfo.makeMessage(" See " + _))
+      throwException(
+        "Error: Called Module() twice without instantiating a Module." +
+          sourceInfo.makeMessage(" See " + _)
+      )
     }
     Builder.readyForModuleConstr = true
 
@@ -38,7 +39,7 @@ object Module extends SourceInfoDoc {
     val parentWhenStack = Builder.whenStack
 
     // Save then clear clock and reset to prevent leaking scope, must be set again in the Module
-    val (saveClock, saveReset)  = (Builder.currentClock, Builder.currentReset)
+    val (saveClock, saveReset) = (Builder.currentClock, Builder.currentReset)
     val savePrefix = Builder.getPrefix
     Builder.clearPrefix()
     Builder.currentClock = None
@@ -49,19 +50,21 @@ object Module extends SourceInfoDoc {
     //   - unset readyForModuleConstr
     //   - reset whenStack to be empty
     //   - set currentClockAndReset
-    val module: T = bc  // bc is actually evaluated here
+    val module: T = bc // bc is actually evaluated here
 
     if (Builder.whenDepth != 0) {
       throwException("Internal Error! when() scope depth is != 0, this should have been caught!")
     }
     if (Builder.readyForModuleConstr) {
-      throwException("Error: attempted to instantiate a Module, but nothing happened. " +
-                     "This is probably due to rewrapping a Module instance with Module()." +
-                     sourceInfo.makeMessage(" See " + _))
+      throwException(
+        "Error: attempted to instantiate a Module, but nothing happened. " +
+          "This is probably due to rewrapping a Module instance with Module()." +
+          sourceInfo.makeMessage(" See " + _)
+      )
     }
     Builder.currentModule = parent // Back to parent!
     Builder.whenStack = parentWhenStack
-    Builder.currentClock = saveClock   // Back to clock and reset scope
+    Builder.currentClock = saveClock // Back to clock and reset scope
     Builder.currentReset = saveReset
 
     // Only add the component if the module generates one
@@ -84,17 +87,22 @@ object Module extends SourceInfoDoc {
 
   /** Returns the implicit Clock */
   def clock: Clock = Builder.forcedClock
+
   /** Returns the implicit Reset */
   def reset: Reset = Builder.forcedReset
+
   /** Returns the current Module */
   def currentModule: Option[BaseModule] = Builder.currentModule
 
-  private[chisel3] def do_pseudo_apply[T <: BaseModule](bc: => T)
-                               (implicit sourceInfo: SourceInfo,
-                                         compileOptions: CompileOptions): T = {
+  private[chisel3] def do_pseudo_apply[T <: BaseModule](
+    bc: => T
+  )(
+    implicit sourceInfo: SourceInfo,
+    compileOptions:      CompileOptions
+  ): T = {
     val parent = Builder.currentModule
 
-    val module: T = bc  // bc is actually evaluated here
+    val module: T = bc // bc is actually evaluated here
 
     module
   }
@@ -150,12 +158,12 @@ abstract class Module(implicit moduleCompileOptions: CompileOptions) extends Raw
   }
 }
 
-
 package experimental {
 
   import chisel3.internal.requireIsChiselType // Fix ambiguous import
 
   object IO {
+
     /** Constructs a port for the current Module
       *
       * This must wrap the datatype used to set the io field of any Module.
@@ -170,20 +178,21 @@ package experimental {
       * requested (so that all calls to ports will return the same information).
       * Internal API.
       */
-    def apply[T<:Data](iodef: T): T = {
+    def apply[T <: Data](iodef: T): T = {
       val module = Module.currentModule.get // Impossible to fail
       require(!module.isClosed, "Can't add more ports after module close")
       requireIsChiselType(iodef, "io type")
 
       // Clone the IO so we preserve immutability of data types
-      val iodefClone = try {
-        iodef.cloneTypeFull
-      } catch {
-        // For now this is going to be just a deprecation so we don't suddenly break everyone's code
-        case e: AutoClonetypeException =>
-          Builder.deprecated(e.getMessage, Some(s"${iodef.getClass}"))
-          iodef
-      }
+      val iodefClone =
+        try {
+          iodef.cloneTypeFull
+        } catch {
+          // For now this is going to be just a deprecation so we don't suddenly break everyone's code
+          case e: AutoClonetypeException =>
+            Builder.deprecated(e.getMessage, Some(s"${iodef.getClass}"))
+            iodef
+        }
       module.bindIoInPlace(iodefClone)
       iodefClone
     }
@@ -192,9 +201,10 @@ package experimental {
 
 package internal {
   import chisel3.experimental.BaseModule
-  import chisel3.experimental.hierarchy.{IsInstantiable, Proto, Clone}
+  import chisel3.experimental.hierarchy.{Clone, IsInstantiable, Proto}
 
   object BaseModule {
+
     /** Represents a clone of an underlying object. This is used to support CloneModuleAsRecord and Instance/Definition.
       *
       * @note We don't actually "clone" anything in the traditional sense but is a placeholder so we lazily clone internal state
@@ -217,7 +227,7 @@ package internal {
     }
 
     // Private internal class to serve as a _parent for Data in cloned ports
-    private[chisel3] class ModuleClone[T <: BaseModule] (val getProto: T) extends PseudoModule with IsClone[T] {
+    private[chisel3] class ModuleClone[T <: BaseModule](val getProto: T) extends PseudoModule with IsClone[T] {
       override def toString = s"ModuleClone(${getProto})"
       def getPorts = _portsRecord
       // ClonePorts that hold the bound ports for this module
@@ -226,7 +236,7 @@ package internal {
       // This is necessary for correctly supporting .toTarget on a Module Clone. If it is made from the
       // Instance/Definition API, it should return an instanceTarget. If made from CMAR, it should return a
       // ModuleTarget.
-      private[chisel3]    var _madeFromDefinition: Boolean = false
+      private[chisel3] var _madeFromDefinition: Boolean = false
       // Don't generate a component, but point to the one for the cloned Module
       private[chisel3] def generateComponent(): Option[Component] = {
         require(!_closed, "Can't generate module more than once")
@@ -248,14 +258,14 @@ package internal {
       private[chisel3] def setRefAndPortsRef(namespace: Namespace): Unit = {
         val record = _portsRecord
         // Use .forceName to re-use default name resolving behavior
-        record.forceName(None, default=this.desiredName, namespace)
+        record.forceName(None, default = this.desiredName, namespace)
         // Now take the Ref that forceName set and convert it to the correct Arg
         val instName = record.getRef match {
           case Ref(name) => name
-          case bad => throwException(s"Internal Error! Cloned-module Record $record has unexpected ref $bad")
+          case bad       => throwException(s"Internal Error! Cloned-module Record $record has unexpected ref $bad")
         }
         // Set both the record and the module to have the same instance name
-        record.setRef(ModuleCloneIO(getProto, instName), force=true) // force because we did .forceName first
+        record.setRef(ModuleCloneIO(getProto, instName), force = true) // force because we did .forceName first
         this.setRef(Ref(instName))
       }
     }
@@ -269,7 +279,9 @@ package internal {
       * @note In addition, the instance name of an InstanceClone is going to be the SAME as the proto, but this is not true
       * for ModuleClone.
       */
-    private[chisel3] final class InstanceClone[T <: BaseModule] (val getProto: T, val instName: () => String) extends PseudoModule with IsClone[T] {
+    private[chisel3] final class InstanceClone[T <: BaseModule](val getProto: T, val instName: () => String)
+        extends PseudoModule
+        with IsClone[T] {
       override def toString = s"InstanceClone(${getProto})"
       // No addition components are generated
       private[chisel3] def generateComponent(): Option[Component] = None
@@ -291,7 +303,7 @@ package internal {
       * target whose root is the Definition. This DefinitionClone is used to represent the root parent of the
       * InstanceClone (which represents the returned module).
       */
-    private[chisel3] class DefinitionClone[T <: BaseModule] (val getProto: T) extends PseudoModule with IsClone[T] {
+    private[chisel3] class DefinitionClone[T <: BaseModule](val getProto: T) extends PseudoModule with IsClone[T] {
       override def toString = s"DefinitionClone(${getProto})"
       // No addition components are generated
       private[chisel3] def generateComponent(): Option[Component] = None
@@ -313,13 +325,18 @@ package internal {
       * @note These are not true Data (the Record doesn't correspond to anything in the emitted
       * FIRRTL yet its elements *do*) so have some very specialized behavior.
       */
-    private[chisel3] class ClonePorts (elts: Data*)(implicit compileOptions: CompileOptions) extends Record {
+    private[chisel3] class ClonePorts(elts: Data*)(implicit compileOptions: CompileOptions) extends Record {
       val elements = ListMap(elts.map(d => d.instanceName -> d.cloneTypeFull): _*)
       def apply(field: String) = elements(field)
       override def cloneType = (new ClonePorts(elts: _*)).asInstanceOf[this.type]
     }
 
-    private[chisel3] def cloneIORecord(proto: BaseModule)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): ClonePorts = {
+    private[chisel3] def cloneIORecord(
+      proto: BaseModule
+    )(
+      implicit sourceInfo: SourceInfo,
+      compileOptions:      CompileOptions
+    ): ClonePorts = {
       require(proto.isClosed, "Can't clone a module before module close")
       // Fake Module to serve as the _parent of the cloned ports
       // We make this before clonePorts because we want it to come up first in naming in
@@ -353,11 +370,12 @@ package experimental {
 
   object BaseModule {
     implicit class BaseModuleExtensions[T <: BaseModule](b: T) {
-      import chisel3.experimental.hierarchy.{Instance, Definition}
-      def toInstance: Instance[T] = new Instance(Proto(b))
+      import chisel3.experimental.hierarchy.{Definition, Instance}
+      def toInstance:   Instance[T] = new Instance(Proto(b))
       def toDefinition: Definition[T] = new Definition(Proto(b))
     }
   }
+
   /** Abstract base class for Modules, an instantiable organizational unit for RTL.
     */
   // TODO: seal this?
@@ -461,30 +479,34 @@ package experimental {
       val baseName = this.getClass.getName
 
       /* A sequence of string filters applied to the name */
-      val filters: Seq[String => String] = Seq(
-        ((a: String) => raw"\$$+anon".r.replaceAllIn(a, "_Anon")) // Merge the "$$anon" name with previous name
-      )
+      val filters: Seq[String => String] =
+        Seq(((a: String) => raw"\$$+anon".r.replaceAllIn(a, "_Anon")) // Merge the "$$anon" name with previous name
+        )
 
       filters
-        .foldLeft(baseName){ case (str, filter) => filter(str) } // 1. Apply filters to baseName
-        .split("\\.|\\$")                                        // 2. Split string at '.' or '$'
-        .filterNot(_.forall(_.isDigit))                          // 3. Drop purely numeric names
-        .last                                                    // 4. Use the last name
+        .foldLeft(baseName) { case (str, filter) => filter(str) } // 1. Apply filters to baseName
+        .split("\\.|\\$") // 2. Split string at '.' or '$'
+        .filterNot(_.forall(_.isDigit)) // 3. Drop purely numeric names
+        .last // 4. Use the last name
     }
 
     /** Legalized name of this module. */
-    final lazy val name = try {
-      // PseudoModules are not "true modules" and thus should share
-      // their original modules names without uniquification
-      this match {
-        case _: PseudoModule => desiredName
-        case _ => Builder.globalNamespace.name(desiredName)
+    final lazy val name =
+      try {
+        // PseudoModules are not "true modules" and thus should share
+        // their original modules names without uniquification
+        this match {
+          case _: PseudoModule => desiredName
+          case _ => Builder.globalNamespace.name(desiredName)
+        }
+      } catch {
+        case e: NullPointerException =>
+          throwException(
+            s"Error: desiredName of ${this.getClass.getName} is null. Did you evaluate 'name' before all values needed by desiredName were available?",
+            e
+          )
+        case t: Throwable => throw t
       }
-    } catch {
-      case e: NullPointerException => throwException(
-        s"Error: desiredName of ${this.getClass.getName} is null. Did you evaluate 'name' before all values needed by desiredName were available?", e)
-      case t: Throwable => throw t
-    }
 
     /** Returns a FIRRTL ModuleName that references this object
       *
@@ -497,8 +519,10 @@ package experimental {
       * @note Should not be called until circuit elaboration is complete
       */
     final def toTarget: ModuleTarget = this match {
-      case m: internal.BaseModule.InstanceClone[_] => throwException(s"Internal Error! It's not legal to call .toTarget on an InstanceClone. $m")
-      case m: internal.BaseModule.DefinitionClone[_] => throwException(s"Internal Error! It's not legal to call .toTarget on an DefinitionClone. $m")
+      case m: internal.BaseModule.InstanceClone[_] =>
+        throwException(s"Internal Error! It's not legal to call .toTarget on an InstanceClone. $m")
+      case m: internal.BaseModule.DefinitionClone[_] =>
+        throwException(s"Internal Error! It's not legal to call .toTarget on an DefinitionClone. $m")
       case _ => ModuleTarget(this.circuitName, this.name)
     }
 
@@ -514,10 +538,13 @@ package experimental {
       * the correct [[InstanceTarget]]s whenever using the Definition/Instance API.
       */
     private[chisel3] def getTarget: IsModule = this match {
-      case m: internal.BaseModule.InstanceClone[_] if m._parent.nonEmpty => m._parent.get.getTarget.instOf(instanceName, name)
-      case m: internal.BaseModule.ModuleClone[_] if m._madeFromDefinition => m._parent.get.getTarget.instOf(instanceName, name)
+      case m: internal.BaseModule.InstanceClone[_] if m._parent.nonEmpty =>
+        m._parent.get.getTarget.instOf(instanceName, name)
+      case m: internal.BaseModule.ModuleClone[_] if m._madeFromDefinition =>
+        m._parent.get.getTarget.instOf(instanceName, name)
       // Without this, we get the wrong CircuitName for the Definition
-      case m: internal.BaseModule.DefinitionClone[_] if m._circuit.nonEmpty => ModuleTarget(this._circuit.get.circuitName, this.name)
+      case m: internal.BaseModule.DefinitionClone[_] if m._circuit.nonEmpty =>
+        ModuleTarget(this._circuit.get.circuitName, this.name)
       case _ => this.toTarget
     }
 
@@ -528,7 +555,7 @@ package experimental {
     final def toAbsoluteTarget: IsModule = {
       _parent match {
         case Some(parent) => parent.toAbsoluteTarget.instOf(this.instanceName, name)
-        case None =>
+        case None         =>
           // FIXME Special handling for Views - evidence of "weirdness" of .toAbsoluteTarget
           // In theory, .toAbsoluteTarget should not be necessary, .toTarget combined with the
           // target disambiguation in FIRRTL's deduplication transform should ensure that .toTarget
@@ -619,17 +646,19 @@ package experimental {
         data match {
           case data: Element if insideCompat => data._assignCompatibilityExplicitDirection
           case data: Element => // Not inside a compatibility Bundle, nothing to be done
-          case data: Aggregate => data.specifiedDirection match {
-            // Recurse into children to ensure explicit direction set somewhere
-            case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => data match {
-              case record: Record =>
-                val compatRecord = !record.compileOptions.dontAssumeDirectionality
-                record.getElements.foreach(assignCompatDir(_, compatRecord))
-              case vec: Vec[_] =>
-                vec.getElements.foreach(assignCompatDir(_, insideCompat))
+          case data: Aggregate =>
+            data.specifiedDirection match {
+              // Recurse into children to ensure explicit direction set somewhere
+              case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip =>
+                data match {
+                  case record: Record =>
+                    val compatRecord = !record.compileOptions.dontAssumeDirectionality
+                    record.getElements.foreach(assignCompatDir(_, compatRecord))
+                  case vec: Vec[_] =>
+                    vec.getElements.foreach(assignCompatDir(_, insideCompat))
+                }
+              case SpecifiedDirection.Input | SpecifiedDirection.Output => // forced assign, nothing to do
             }
-            case SpecifiedDirection.Input | SpecifiedDirection.Output => // forced assign, nothing to do
-          }
         }
       }
 
@@ -669,10 +698,12 @@ package experimental {
 
     /** Signal name (for simulation). */
     override def instanceName: String =
-      if (_parent == None) name else _component match {
-        case None => getRef.name
-        case Some(c) => getRef fullName c
-      }
+      if (_parent == None) name
+      else
+        _component match {
+          case None    => getRef.name
+          case Some(c) => getRef.fullName(c)
+        }
 
   }
 }