diff options
| author | Jack Koenig | 2020-10-12 21:02:27 -0700 |
|---|---|---|
| committer | Jack Koenig | 2021-02-09 17:28:07 -0800 |
| commit | 0a0d7c6aac4326f2127d6d95efa5a4e10c81946c (patch) | |
| tree | 89a42cf3ae9eb96b02a54bc83040c04cd1ea294d /core/src/main/scala/chisel3/Element.scala | |
| parent | 53b620478ddab1faa96512e473fa198f7f1fcf50 (diff) | |
Make it possible to GC Data instances
No longer create a pointer from parent to every HasId, only do it by
default for BaseModules and MemBases. Add pointer from parent to Data
upon binding the Data.
* Add MemTypeBinding for port types of Mems
This binding is similar to the SampleElementBinding for Vecs in that
these Data are not truly hardware, but are represented in the FIRRTL IR
and thus need some representation.
* Call _onModuleClose on unbound Records
This maintains some corner-case behavior that is nevertheless relied
upon. It ensures that refs are set for the elements of Records, even if
they are not bound to any real hardware.
Diffstat (limited to 'core/src/main/scala/chisel3/Element.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/Element.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Element.scala b/core/src/main/scala/chisel3/Element.scala index 55415f3d..0c99ff70 100644 --- a/core/src/main/scala/chisel3/Element.scala +++ b/core/src/main/scala/chisel3/Element.scala @@ -17,7 +17,8 @@ abstract class Element extends Data { def widthKnown: Boolean = width.known def name: String = getRef.name - private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { + private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection): Unit = { + _parent.foreach(_.addId(this)) binding = target val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection) direction = ActualDirection.fromSpecified(resolvedDirection) |