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| author | Jack | 2022-04-26 02:53:08 +0000 |
|---|---|---|
| committer | Jack | 2022-04-26 02:53:08 +0000 |
| commit | 3a6cc75d72cbf890bbd45a002c31d16abfc6896d (patch) | |
| tree | 298a39cbdbcd7e89953d75dbd840884f29ff7699 /core/src/main/scala/chisel3/Clock.scala | |
| parent | be1ac06bf20c6c3d84c8ce5b0a50e2980e546e7e (diff) | |
| parent | d5a964f6e7beea1f38f9623224fc65e2397e1fe7 (diff) | |
Merge branch '3.5.x' into 3.5-release
Diffstat (limited to 'core/src/main/scala/chisel3/Clock.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/Clock.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Clock.scala b/core/src/main/scala/chisel3/Clock.scala index 68174d7c..64e91c42 100644 --- a/core/src/main/scala/chisel3/Clock.scala +++ b/core/src/main/scala/chisel3/Clock.scala @@ -23,7 +23,7 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match { - case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions) + case _: Clock | DontCare => super.connect(that)(sourceInfo, connectCompileOptions) case _ => super.badConnect(that)(sourceInfo) } |