diff options
| author | Schuyler Eldridge | 2018-12-11 17:49:20 -0500 |
|---|---|---|
| committer | GitHub | 2018-12-11 17:49:20 -0500 |
| commit | 9ce6d7de1510a9d73c718acc475f1000a9979e56 (patch) | |
| tree | 952d91488b12b07831104b2f36c148f5fee6c500 /chiselFrontend | |
| parent | 6a0cffec5a23dd87e4386fc50683b7945113fc9f (diff) | |
| parent | 4b05f9e8e5821272dee25628b77fc24314d438f0 (diff) | |
Merge pull request #961 from freechipsproject/subwrap
Improve quality of code generation for UInt.-%
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index 7e98cf04..b5de1317 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -738,10 +738,10 @@ sealed class UInt private[core] (width: Width) extends Bits(width) with Num[UInt (this +& that).tail(1) /** @group SourceInfoTransformMacro */ def do_-& (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - binop(sourceInfo, SInt((this.width max that.width) + 1), SubOp, that).asUInt + (this subtractAsSInt that).asUInt /** @group SourceInfoTransformMacro */ def do_-% (that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = - (this -& that).tail(1) + (this subtractAsSInt that).tail(1) /** Bitwise and operator * @@ -913,6 +913,9 @@ sealed class UInt private[core] (width: Width) extends Bits(width) with Num[UInt compileOptions: CompileOptions): Unit = { this := that.asUInt } + + private def subtractAsSInt(that: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): SInt = + binop(sourceInfo, SInt((this.width max that.width) + 1), SubOp, that) } // This is currently a factory because both Bits and UInt inherit it. |
