diff options
| author | Richard Lin | 2018-07-03 16:01:04 -0600 |
|---|---|---|
| committer | Richard Lin | 2018-07-04 18:39:28 -0500 |
| commit | 46f0aa3a779f433c95fd6d8885572d7a0b827015 (patch) | |
| tree | 37db567010fe0f292e9a32e6273ea94d5ab9632e /chiselFrontend | |
| parent | ffb87e99c5c0c6c5864293092f942be33206de22 (diff) | |
Remove forceName rom BlackBox/ExtModule, filter out forceName in UserModule
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 2 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/UserModule.scala | 10 |
2 files changed, 7 insertions, 5 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index ff54e9e6..3e7251c5 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -70,7 +70,6 @@ abstract class ExtModule(val params: Map[String, Param] = Map.empty[String, Para // While BlackBoxes are not supposed to have an implementation, we still need to call // _onModuleClose on all nodes (for example, Aggregates use it for recursive naming). for (id <- getIds) { - id.forceName(default="_T", _namespace) id._onModuleClose } @@ -155,7 +154,6 @@ abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param // Doing so would cause the wrong names to be assigned, since their parent // is now the module itself instead of the io bundle. for (id <- getIds; if id ne io) { - id.forceName(default="_T", _namespace) id._onModuleClose } diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala index 831b3707..422760ec 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala @@ -72,7 +72,11 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions) for (id <- getIds) { id match { case id: BaseModule => id.forceName(default=id.desiredName, _namespace) - case id => id.forceName(default="_T", _namespace) + case id: Data => id.topBinding match { + case OpBinding(_) | MemoryPortBinding(_) | PortBinding(_) | RegBinding(_) | WireBinding(_) => + id.forceName(default="_T", _namespace) + case _ => + } } id._onModuleClose } @@ -156,11 +160,11 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) @chiselRuntimeDeprecated @deprecated("Module constructor with override _clock deprecated, use withClock", "chisel3") def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions) - + @chiselRuntimeDeprecated @deprecated("Module constructor with override _reset deprecated, use withReset", "chisel3") def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(None, Option(_reset))(moduleCompileOptions) - + @chiselRuntimeDeprecated @deprecated("Module constructor with override _clock, _reset deprecated, use withClockAndReset", "chisel3") def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions) |
