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| author | Schuyler Eldridge | 2019-01-11 15:55:59 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2019-05-22 16:17:17 -0400 |
| commit | 325e48809587fdf47d398578a1d94f856ab1f275 (patch) | |
| tree | 8607f572ea9532de7487a169a3d5694804dbf5a5 /chiselFrontend | |
| parent | 4c48d5a94f9242f471e4c1ad39c664c672eafe13 (diff) | |
Add chisel3.stage.phases.Convert Phase
This coalesces three distinct operations into one Convert Phase:
1. Chisel Circuit to FIRRTL Circuit (CHIRRTL) conversion
2. Conversion of Chisel Annotations to FIRRTL Annotations
3. Generation of RunFirrtlTransformAnnotations
Co-Authored-By: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-Authored-By: chick <chick@qrhino.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'chiselFrontend')
0 files changed, 0 insertions, 0 deletions