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| author | jackkoenig | 2016-05-20 13:38:18 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-05-20 13:38:18 -0700 |
| commit | d7697eb14a0195cc3726bf45fdf38c631b6f6507 (patch) | |
| tree | 7b9372829fd9167e6d15d7f5323f6dfd4e5b11f4 /chiselFrontend/src | |
| parent | a26a0ad4504e99182e3548db8f407c3dad7302b0 (diff) | |
Update BackendCompilationUtilities.verilogToCpp to specify top-module
This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.
Diffstat (limited to 'chiselFrontend/src')
0 files changed, 0 insertions, 0 deletions