move doNotDedup to experimental (#1008)

1 files changed, 49 insertions, 1 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
index 93a02139..b2c9ea78 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
@@ -5,9 +5,10 @@ package chisel3.core
 import scala.language.existentials
 
 import chisel3.internal.{Builder, InstanceId}
+import chisel3.core.ImplicitModule
 import firrtl.Transform
 import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName}
-import firrtl.transforms.DontTouchAnnotation
+import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation}
 
 /** Interface for Annotations in Chisel
   *
@@ -88,3 +89,50 @@ object dontTouch { // scalastyle:ignore object.name
   }
 }
 
+/** Marks that a module to be ignored in Dedup Transform in Firrtl pass
+  *
+  * @example {{{
+  *  def fullAdder(a: UInt, b: UInt, myName: String): UInt = {
+  *    val m = Module(new Module {
+  *      val io = IO(new Bundle {
+  *        val a = Input(UInt(32.W))
+  *        val b = Input(UInt(32.W))
+  *        val out = Output(UInt(32.W))
+  *      })
+  *      override def desiredName = s"adder_$myNname"
+  *      io.out := io.a + io.b
+  *    })
+  *    doNotDedup(m)
+  *    m.io.a := a
+  *    m.io.b := b
+  *    m.io.out
+  *  }
+  *
+  *class AdderTester extends Module
+  *  with ConstantPropagationTest {
+  *  val io = IO(new Bundle {
+  *    val a = Input(UInt(32.W))
+  *    val b = Input(UInt(32.W))
+  *    val out = Output(Vec(2, UInt(32.W)))
+  *  })
+  *
+  *  io.out(0) := fullAdder(io.a, io.b, "mod1")
+  *  io.out(1) := fullAdder(io.a, io.b, "mod2")
+  * }
+  * }}}
+  *
+  * @note Calling this on [[Data]] creates an annotation that Chisel emits to a separate annotations
+  * file. This file must be passed to FIRRTL independently of the `.fir` file. The execute methods
+  * in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically.
+  */
+
+object doNotDedup { // scalastyle:ignore object.name
+  /** Marks a module to be ignored in Dedup Transform in Firrtl
+    *
+    * @param data The module to be marked
+    * @return Unmodified signal `module`
+    */
+   def apply[T <: LegacyModule](module: T)(implicit compileOptions: CompileOptions): Unit = {
+    annotate(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(module.toNamed) })
+  }
+}