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authorRichard Lin2018-07-04 17:13:04 -0500
committerRichard Lin2018-07-04 18:39:28 -0500
commit5c32cd87b85e2607e558f286cb1f8fd9604e4c83 (patch)
treef0c1ecf7310c3300d5f4372b601b356487084fa4 /chiselFrontend/src
parentf75366ce5c9d6c676f27aa7980637cb118a520bd (diff)
Change wording of internal failure
Diffstat (limited to 'chiselFrontend/src')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Bits.scala2
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index b54b5e11..b67c3fe3 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -94,7 +94,7 @@ sealed abstract class Bits(width: Width)
case Some(ElementLitBinding(litArg)) => litArg
case Some(BundleLitBinding(litMap)) => litMap.get(this) match {
case Some(litArg) => litArg
- case _ => throwException(s"internal error: DontCare should be caught before connect")
+ case _ => throwException(s"internal error: DontCare should be caught before getting ref")
}
case _ => super.ref
}