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authorJack Koenig2018-04-22 13:18:30 -0700
committerGitHub2018-04-22 13:18:30 -0700
commit297e9fa813595b10ef154def2ee5fcce2934837d (patch)
tree0f8dc144fde04a23f0504d40b90c92d23a841b79 /chiselFrontend/src
parenta86e38889302662db14b932e4e0d862290c01308 (diff)
Add Module.currentModule for getting a reference to the current Module (#810)
Resolves #809
Diffstat (limited to 'chiselFrontend/src')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 5a4f6abb..2f365dd7 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -75,6 +75,8 @@ object Module {
def clock: Clock = Builder.forcedClock
/** Returns the implicit Reset */
def reset: Reset = Builder.forcedReset
+ /** Returns the current Module */
+ def currentModule: Option[BaseModule] = Builder.currentModule
}
/** Abstract base class for Modules, an instantiable organizational unit for RTL.