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authorAndrew Waterman2019-03-15 16:38:46 -0700
committerGitHub2019-03-15 16:38:46 -0700
commitcfb2f08db9d9df121a82f138dd71297dbcea66cc (patch)
tree08bf92d133f5e05e155878fcbd64e41cee892a6d /chiselFrontend/src/main
parentab68f5d76f645b721614f0efa8d55ab7d1e08a3d (diff)
parentd3280685892bbf0fd9b3c0f3d9e6750a30d25593 (diff)
Merge pull request #1033 from freechipsproject/popcount
Tighten inferred width for PopCount
Diffstat (limited to 'chiselFrontend/src/main')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala4
1 files changed, 3 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index e87fb045..f15fb178 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -37,7 +37,9 @@ private[chisel3] object SeqUtils {
def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = in.size match {
case 0 => 0.U
case 1 => in.head
- case n => count(in take n/2) +& count(in drop n/2)
+ case n =>
+ val sum = count(in take n/2) +& count(in drop n/2)
+ sum(BigInt(n).bitLength - 1, 0)
}
/** Returns the data value corresponding to the first true predicate.